Texas Instruments TNETX4090 specifications Reading Rdram, Internal wrap test

Page 58

TNETX4090

ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNETSWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

reading RDRAM

Reading from RDRAM memory is accomplished as follows:

1.Write the byte address for the access to ramaddress in RAMAddress.

2.Set rdwrite = 1 and rdram = 1 (these can be written simultaneously).

3.Poll rdram until it becomes 0. This indicates that the read has completed.

4.Read the data for the access to RAMData. Up to 64 bytes can be read, provided that all but the six least significant bits of the address are the same for all the data. Inc in RAMAddress can be used to autoincrement the address.

internal wrap test

Internal wrap mode causes some or all of the Ethernet MACs to be configured to loop back transmitted data into the receive path. This allows a frame to be sent into a designated source port and then selectively routed successively to and from ports involved in the test, before finally transmitting the frame out of the original port. By varying the number of ports between which the frame is forwarded, the potential fault capture area is expanded or constrained.

Intwrap in SysTest determines which ports loop back. Ports 0 or 8 can be configured to not loop back, allowing them to be used as the start/end port for the test. Alternatively, the NM port (accessed via DIO) can be used for this purpose, with all MII ports configured to loop back.

For a frame to be forwarded from one port to another in this fashion, the switch must be programmed as follows:

DAssign a unique VID to each of the PortxQTag registers, and program these tags into the VLANnQID registers.

DThe VLANnPorts register associated with each of the VLANnQID registers should have only one bit set, indicating to which port frames containing that IEEE Std 802.3 tag should be routed.

DRxacc and Txacc for each port must be 1. This causes the port to add the VID from its PortxQTag to the frame on reception, and strip the tag before transmission.

DThe destination address of the frames to be applied is not known, and UnkUniPorts and UnkMultiPorts should be all 1s.

This causes the following:

1.The VID from the source port PortxQTag register is added to the frame upon reception. As the address of the frame is unknown, it is forwarded to the AND of the appropriate VLANnPorts and UnkUniPorts (unicast) or UnkMultiPorts (multicast). As VLANnPorts should contain only a single 1, this should be a single port.

2.The frame is transmitted from the destination port selected in 1. Its VLAN tag is stripped beforehand; the frame loops back to the receive path.

3.Steps 1 and 2 are repeated, but the VID added upon reception is different from the one just stripped off at transmission. This means a different VLANnPorts register is used to determine the destination.

The port order shown here is sequential, but the actual order depends on how ports are paired in the VLANnPorts registers, and how the PortxQTag registers are assigned.

4.Eventually, the frame is sent to a port that is not configured for loopback, and leaves the switch.

58

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Page 57 Page 59
Image 58
Page 57 Page 59
Contents Description MAC Eeprom CPU I/F MIIMAC MII DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball NameReset Sdma SAD0 Control logic interface Terminal FunctionsJtag interface Terminal Internal Description Name RESISTOR²100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 PulldownM00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4MII management interface Rdram interface DIO interface Eeprom interfaceLED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports Port no Head Statistic Tail 0x90ExAddress-Lookup Statistics DMA Interface SignalsSignal Description Receiving/transmitting management framesDIO Interface State During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portTpid TCI Vlan IDFCS CRCTNETX4090 NM bandwidth and priority PHY management interfaceFull-duplex NM port Interrupt processingMAC interface Backoff Adaptive performance optimization APOInterframe gap enforcement Receive versus transmit priority10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Full-duplex hardware flow control Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode OutcomePretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN Learning Format Receive Pretag Bit Definitions Transmit Pretag Bit DefinitionsPretag on reception BIT Name FunctionRXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology TNETX4090 RXD Flow COL TXDRing-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Collision LED States Compatibility with future device revisionsPort LED States State DisplayLamp test PCS duplex LEDLED Status Bit Definitions and Shift Order Multi-LED displayTNETX4090 VCC NC Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN Sout SCHAIN0 Txclk Vref Rxclk VDDRacbist instruction Jtag Instruction OpcodesHighz instruction Jtag Bist StatusVlan support Frame routingIale Ieee Std 802.1Q header ± transmission Address maintenanceIeee Std 802.1Q tags ± reception Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source portTrunk Group 1 Port Membership Trunk1Ports Register Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Extended port awarenessFlow control Multicast limit Other flow-control mechanismsHardware flow control System test capabilitiesReading Rdram Internal wrap testDuplex wrap test PHY TNETX4090Recommended operating conditions MIN NOM MAX UnitReset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions Physical medium attachment interface port Receive PMA receive see FigureTransmit PMA transmit see FigureGmii receive see Figure Gmii portGmii transmit see Figure PMA and Gmii clock see Figure Gmii ClockMII ports 0±8 MII receive see FigureMII transmit see Figure MII clock see FigureDtxclk Drxclk Rdram interfaceRdram see Figure Dbusctrl DbusenDIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 SrdyEeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOH VOLTTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TNETX4090GGP Obsolete BGA TBDImportant Notice
Top Page Image Contents