Texas Instruments TNETX4090 specifications Frame-Routing Algorithm

Page 51

TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

Start

Key:

UnkVLAN

interrupt

Known

No

VLAN?

statistic

Unkmem

Yes

No

Source Port = 1 in.

VLANnPorts?

Yes

Yes

Destination

No

Address

Found?

Yes

Destination

No

Destination

Destination

No

Destination

No

Locked

is

is

is

Bit = 1?

Multicast?

Multicast?

Multicast?

No

Yes

Yes

Yes

Source

Port

Source Port

Source Port

Source

Port

Source Port

Yes

Blocked by

Blocked by

Blocked by

Blocked by

Blocked by

RxUniBlockPorts

RxMultiBlockPorts

RxMultiBlockPorts?

RxUniBlockPorts?

RxMultiBlockPorts or

and Dest.

and Dest.

UnkVLAN=0?

Nblck=0?

Yes

Nblck=0?

Yes

Yes

Yes

No

No

No

No

No

Port Routing

Port Routing

Port Routing

Port Routing

Port Routing

Code = Port Code

Code = Port Vector

Code =

Code =

Code =

From Records

From Records

UnkMultiPorts

UnkUniPorts

UnkVLANPort

Unknown

Unknown

Multicast

Unlcast

Set Port Routing

Destination

Destination

Code to 0

Destination

Yes

Include UplinkPort

AND Port Routing

in Port

Code With VLAN

Cuplink Bit

Routing Code

VLANnPorts Code

Set?

No

To C

To A

To B

(Continued)

(Continued)

(Continued)

Figure 12. Frame-Routing Algorithm

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Image 51

Contents Description DMA MIIMAC MII MAC Eeprom CPU I/FPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted AlphabeticallyReset Sdma SAD0 Terminal Internal Description Name RESISTOR² Terminal FunctionsJtag interface Control logic interfaceM08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii modeTerminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SwitchMII management interface Rdram interface Eeprom interface DIO interfacePower supply LED interface100-/1000-Mbit/s port PCS LED interface DIO interface description DIO Internal Register Address MapByte DIO Address TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNETVLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port Statistics TailPort no Head Statistic Even ODD Ports 0x90Ex Port no Head Statistic TailReceiving/transmitting management frames DMA Interface SignalsSignal Description Address-Lookup StatisticsIeee Std 802.1Q Vlan tags on the NM port State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset DIO Interface State During Hardware ResetCRC Vlan IDFCS Tpid TCITNETX4090 Interrupt processing PHY management interfaceFull-duplex NM port NM bandwidth and priorityMAC interface Receive versus transmit priority Adaptive performance optimization APOInterframe gap enforcement BackoffSpeed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Outcome Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode Full-duplex hardware flow controlPretagging and extended port awareness Pretag on transmissionM08GTCLK M08TXEN BIT Name Function Transmit Pretag Bit DefinitionsPretag on reception Learning Format Receive Pretag Bit DefinitionsTNETX4090 RXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology RXD Flow COL TXDSwitch Terminal Ring-Topology ConnectivityM08GTCLK M08TXEN M08RXDV SCL SDA Edio TNETX4090 EclkGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes State Display Compatibility with future device revisionsPort LED States Collision LED StatesMulti-LED display PCS duplex LEDLED Status Bit Definitions and Shift Order Lamp testSout SCHAIN0 Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN TNETX4090 VCC NC Txclk Vref Rxclk VDDJtag Bist Status Jtag Instruction OpcodesHighz instruction Racbist instructionFrame routing Vlan supportIale Spanning-tree support Address maintenanceIeee Std 802.1Q tags ± reception Ieee Std 802.1Q header ± transmissionAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharingExtended port awareness Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Trunk Group 1 Port Membership Trunk1Ports RegisterFlow control System test capabilities Other flow-control mechanismsHardware flow control Multicast limitInternal wrap test Reading RdramPHY TNETX4090 Duplex wrap testMIN NOM MAX Unit Recommended operating conditionsJtag interface Control signals Reset see FigureTiming requirements over recommended operating conditions PMA receive see Figure Physical medium attachment interface port ReceivePMA transmit see Figure TransmitGmii port Gmii receive see FigureGmii transmit see Figure Gmii Clock PMA and Gmii clock see FigureMII receive see Figure MII ports 0±8MII clock see Figure MII transmit see FigureDbusctrl Dbusen Rdram interfaceRdram see Figure Dtxclk DrxclkDIO interface DIO and DMA writes see FigureSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see FigureEeprom interface Eeprom writes see FigureEeprom reads see Figure LED interface LED see FigureLedclk Leddata VOL VOHTTL Output Macro Propagation-Delay-Time Voltage Waveforms VDD VOH 50% LvcmosVOL VDD Mechanical Data TBD TNETX4090GGP Obsolete BGAImportant Notice