Texas Instruments TNETX4090 Signal-to-Ball Mapping Signal Names Sorted Alphabetically

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TNETX4090

ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNETSWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

Table 1. Signal-to-Ball Mapping (Signal Names Sorted Alphabetically)

SIGNAL

BALL

 

SIGNAL

BALL

 

 

SIGNAL

BALL

 

SIGNAL

BALL

 

SIGNAL

BALL

 

NAME

NO.

 

NAME

NO.

 

 

NAME

NO.

 

NAME

NO.

 

NAME

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DBUS_CTL

Y26

 

GND

AF26

 

M03_CRS

B6

 

M06_RXD2

Y3

 

MDIO

K25

 

DBUS_DATA0

AC26

 

GNDa

U24

 

M03_LINK

A4

 

M06_RXD3

Y4

 

MRESET

 

K24

 

DBUS_DATA1

AA24

 

L08_DPLX

 

 

 

AE18

 

M03_RCLK

C6

 

M06_RXDV

W1

 

NC

A3

 

DBUS_DATA2

AB26

 

LED_CLK

AD19

 

 

M03_RENEG

 

C1

 

M06_RXER

AA2

 

NC

A24

 

DBUS_DATA3

Y24

 

LED_DATA

 

 

AE19

 

M03_RXD0

A5

 

M06_TCLK

T1

 

NC

C23

 

DBUS_DATA4

V24

 

M00-COL

C21

 

M03_RXD1

B5

 

M06_TXD0

U1

 

NC

D2

 

DBUS_DATA5

U25

 

M00_CRS

B21

 

M03_RXD2

C5

 

M06_TXD1

U2

 

NC

D3

 

DBUS_DATA6

U26

 

M00_LINK

B19

 

M03_RXD3

D5

 

M06_TXD2

U3

 

NC

D6

 

DBUS_DATA7

T26

 

M00_RCLK

A21

 

M03_RXDV

C4

 

M06_TXD3

U4

 

NC

D24

 

DBUS_DATA8

R25

 

M00_RENEG

 

C26

 

M03_RXER

B4

 

M06_TXEN

V3

 

NC

D25

 

DBUS_EN

T25

 

M00_RXD0

A20

 

M03_TCLK

A8

 

M06_TXER

V2

 

NC

E1

 

DCCTRL

P24

 

M00_RXD1

B20

 

M03_TXD0

A7

 

M07_COL

AC6

 

NC

E2

 

DRX_CLK

V26

 

M00_RXD2

C20

 

M03_TXD1

B7

 

M07_CRS

AD6

 

NC

E3

 

DTX_CLK

V25

 

M00_RXD3

D20

 

M03_TXD2

C7

 

M07_LINK

AF3

 

NC

E4

 

DVREF

AA26

 

M00_RXDV

D19

 

M03_TXD3

D7

 

M07_RCLK

AE6

 

NC

E23

 

ECLK

L26

 

M00_RXER

C19

 

M03_TXEN

B8

 

M07_RENEG

 

AD1

 

NC

E24

 

EDIO

M26

 

M00_TCLK

B23

 

M03_TXER

C8

 

M07_RXD0

AF7

 

NC

E25

 

FLOW

AF8

 

M00_TXD0

A23

 

M04_COL

H2

 

M07_RXD1

AE7

 

NC

E26

 

GND

A1

 

M00_TXD1

A22

 

M04_CRS

H1

 

M07_RXD2

AD7

 

NC

F4

 

GND

A2

 

M00_TXD2

B22

 

M04_LINK

L3

 

M07_RXD3

AC7

 

NC

F23

 

GND

A13

 

M00_TXD3

C22

 

M04_RCLK

J3

 

M07_RXDV

AC8

 

NC

F24

 

GND

A14

 

M00_TXEN

D22

 

M04_RENEG

 

F3

 

M07_RXER

AD8

 

NC

F25

 

GND

A25

 

M00_TXER

D21

 

M04_RXD0

J1

 

M07_TCLK

AD4

 

NC

F26

 

GND

A26

 

M01_COL

D16

 

M04_RXD1

K1

 

M07_TXD0

AF5

 

NC

G23

 

GND

AF13

 

M01_CRS

C16

 

M04_RXD2

K2

 

M07_TXD1

AE5

 

NC

G24

 

GND

AF14

 

M01_LINK

B14

 

M04_RXD3

K3

 

M07_TXD2

AD5

 

NC

G25

 

GND

B1

 

M01_RCLK

B16

 

M04_RXDV

J2

 

M07_TXD3

AC5

 

NC

G26

 

GND

B3

 

M01_RENEG

 

D26

 

M04_RXER

L4

 

M07_TXEN

AE4

 

NC

H24

 

GND

B24

 

M01_RXD0

A15

 

M04_TCLK

F1

 

M07_TXER

AF4

 

NC

H25

 

GND

B26

 

M01_RXD1

B15

 

M04_TXD0

G1

 

M08_COL

AD12

 

NC

H26

 

GND

C2

 

M01_RXD2

C15

 

M04_TXD1

G2

 

M08_CRS

AC12

 

NC

J24

 

GND

C25

 

M01_RXD3

D15

 

M04_TXD2

G3

 

M08_EWRAP

AE13

 

NC

J25

 

GND

N1

 

M01_RXDV

A16

 

M04_TXD3

G4

 

M08_GTCLK

AF17

 

NC

J26

 

GND

N26

 

M01_RXER

C14

 

M04_TXEN

H4

 

M08_LINK

AE17

 

NC

K23

 

GND

P1

 

M01_TCLK

C17

 

M04_TXER

H3

 

M08_LREF

AF12

 

NC

N23

 

GND

P25

 

M01_TXD0

A19

 

M05_COL

N2

 

M08_MII

AC17

 

NC

N24

 

GND

P26

 

M01_TXD1

A18

 

M05_CRS

P3

 

M08_PMA

 

AD17

 

NC

N25

 

GND

R23

 

M01_TXD2

B18

 

M05_LINK

T2

 

M08_RCLK

AE12

 

NC

AA4

 

GND

R24

 

M01_TXD3

C18

 

M05_RCLK

P2

 

M08_RFCLK

AD13

 

NC

AB1

 

GND

R26

 

M01_TXEN

B17

 

M05_RENEG

 

F2

 

M08_RXD0

AF9

 

NC

AB2

 

GND

T24

 

M01_TXER

A17

 

M05_RXD0

R1

 

M08_RXD1

AE9

 

NC

AB3

 

GND

U23

 

M02_COL

C11

 

M05_RXD1

R2

 

M08_RXD2

AD9

 

NC

AB4

 

GND

W23

 

M02_CRS

B11

 

M05_RXD2

R3

 

M08_RXD3

AF10

 

NC

AB23

 

GND

W24

 

M02_LINK

A9

 

M05_RXD3

R4

 

M08_RXD4

AE10

 

NC

AB24

 

GND

W25

 

M02_RCLK

A11

 

M05_RXDV

T4

 

M08_RXD5

AD10

 

NC

AC1

 

GND

W26

 

M02_RENEG

 

D1

 

M05_RXER

T3

 

M08_RXD6

AF11

 

NC

AC2

 

GND

Y23

 

M02_RXD0

A10

 

M05_TCLK

L2

 

M08_RXD7

AE11

 

NC

AC3

 

GND

Y25

 

M02_RXD1

B10

 

M05_TXD0

M1

 

M08_RXDV

AD11

 

NC

AC24

 

GND

AA23

 

M02_RXD2

C10

 

M05_TXD1

M2

 

M08_RXER

AC11

 

NC

AC25

 

GND

AA25

 

M02_RXD3

D10

 

M05_TXD2

M3

 

M08_TXD0

AF16

 

NC

AD18

 

GND

AB25

 

M02_RXDV

C9

 

M05_TXD3

M4

 

M08_TXD1

AE16

 

NC

AD26

 

GND

AD2

 

M02_RXER

B9

 

M05_TXEN

L1

 

M08_TXD2

AD16

 

NC

AE8

 

GND

AD25

 

M02_TCLK

C13

 

M05_TXER

N3

 

M08_TXD3

AC16

 

NC

AF6

 

GND

AE1

 

M02_TXD0

A12

 

M06_COL

V1

 

M08_TXD4

AF15

 

NC

AF18

 

GND

AE3

 

M02_TXD1

B12

 

M06_CRS

W3

 

M08_TXD5

AE15

 

 

 

 

 

GND

AE24

 

M02_TXD2

C12

 

M06_LINK

AA1

 

M08_TXD6

AD15

 

 

 

 

 

GND

AE26

 

M02_TXD3

D12

 

M06_RCLK

W2

 

M08_TXD7

AC15

 

 

 

 

 

GND

AF1

 

M02_TXEN

B13

 

M06_RENEG

 

AA3

 

M08_TXEN

AE14

 

 

 

 

 

GND

AF2

 

M02_TXER

D11

 

M06_RXD0

Y1

 

M08_TXER

AD14

 

 

 

 

 

GND

AF25

 

M03_COL

A6

 

M06_RXD1

Y2

 

MDCLK

K26

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Image 5
Contents Description MAC MII MIIMAC Eeprom CPU I/F DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted AlphabeticallyReset Sdma SAD0 Jtag interface Terminal FunctionsControl logic interface Terminal Internal Description Name RESISTOR²M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii modeTerminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SwitchMII management interface Rdram interface Eeprom interface DIO interface100-/1000-Mbit/s port PCS LED interface Power supplyLED interface Byte DIO Address DIO interface descriptionDIO Internal Register Address Map TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNETVLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port no Head Statistic Even ODD Ports Port StatisticsTail 0x90Ex Port no Head Statistic TailSignal Description DMA Interface SignalsAddress-Lookup Statistics Receiving/transmitting management framesDIO Interface During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portFCS Vlan IDTpid TCI CRCTNETX4090 Full-duplex NM port PHY management interfaceNM bandwidth and priority Interrupt processingMAC interface Interframe gap enforcement Adaptive performance optimization APOBackoff Receive versus transmit prioritySpeed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Pause Negotiation in MII Mode Port 8 Duplex Negotiation in MII ModeFull-duplex hardware flow control OutcomeM08GTCLK M08TXEN Pretagging and extended port awarenessPretag on transmission Pretag on reception Transmit Pretag Bit DefinitionsLearning Format Receive Pretag Bit Definitions BIT Name FunctionRing-cascade topology Directed Format Receive Pretag Bit DefinitionsRXD Flow COL TXD TNETX4090 RXD Flow COL TXDM08GTCLK M08TXEN M08RXDV Switch TerminalRing-Topology Connectivity GND SCL SDAEdio TNETX4090 Eclk Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Port LED States Compatibility with future device revisionsCollision LED States State DisplayLED Status Bit Definitions and Shift Order PCS duplex LEDLamp test Multi-LED displayBUS Enable GND Rdram BUS Ctrl SIN BUS Enable GND BUS Ctrl Rdram SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDDHighz instruction Jtag Instruction OpcodesRacbist instruction Jtag Bist StatusIale Frame routingVlan support Ieee Std 802.1Q tags ± reception Address maintenanceIeee Std 802.1Q header ± transmission Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharingTrunk Group 0 Port Membership Trunk0Ports Register Port trunking exampleTrunk Group 1 Port Membership Trunk1Ports Register Extended port awarenessFlow control Hardware flow control Other flow-control mechanismsMulticast limit System test capabilitiesInternal wrap test Reading RdramPHY TNETX4090 Duplex wrap testMIN NOM MAX Unit Recommended operating conditionsTiming requirements over recommended operating conditions Jtag interface Control signalsReset see Figure PMA receive see Figure Physical medium attachment interface port ReceivePMA transmit see Figure TransmitGmii transmit see Figure Gmii portGmii receive see Figure Gmii Clock PMA and Gmii clock see FigureMII receive see Figure MII ports 0±8MII clock see Figure MII transmit see FigureRdram see Figure Rdram interfaceDtxclk Drxclk Dbusctrl DbusenSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO interfaceDIO and DMA writes see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see FigureEeprom reads see Figure Eeprom interfaceEeprom writes see Figure Ledclk Leddata LED interfaceLED see Figure VOL VOHTTL Output Macro Propagation-Delay-Time Voltage Waveforms VOL VDD VDD VOH50% Lvcmos Mechanical Data TBD TNETX4090GGP Obsolete BGAImportant Notice