Texas Instruments TNETX4090 specifications Ieee Std 802.1Q tags ± reception, Address maintenance

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TNETX4090

ThunderSWITCH II9-PORT 100-/1000-MBIT/S ETHERNETSWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

IEEE Std 802.1Q tags ± reception

By the time the IALE examines the received frame, it contains an IEEE Std 802.1Q tag header (after the source address). The tag used depends on the port configuration. If the port is configured as an access port, IALE always uses the default VID programmed for this port and assumes that all received frames on this port are untagged. If the frame already contained a tag, it is tagged again. If the port is programmed as a non-access port, the tag added depends on the received frame. If the frame is not tagged or the value of the tag field is 0x000, the default port VID is used to internally tag the frame. Otherwise, the VID contained in the frame is used by the IALE.

The IALE supports 64 of the possible 4096 VIDs that can be encoded within the IEEE Std 802.1Q tag. The VID in the received frame is compared with these 64 VLAN IDs to see which (if any) of them it matches.

unknown VLAN

If there is no match, the rest of the address-lookup process is abandoned. A new VLAN interrupt is provided to the attached CPU. The source address, VLAN ID, and port information is provided in internal registers so that the CPU can determine if it wants to add this VID to the lookup table. If the destination address is unicast, the frame is discarded. If the destination address is a multicast/broadcast, the frame is forwarded based on a programmable port mask.

known VLAN

If there is a match, the VLAN index associated with this VID, together with the destination and source address, are forwarded to the address lookup and subsequent routing process. (Only one of the VIDs matches if they have been programmed correctly. If more than one matches, the hardware chooses one of them.)

new VLAN member

The IALE checks to see if the source port already has been declared as a member of this VLAN. If not, an interrupt is provided to allow the attached CPU to add this port as a new member of the VLAN.

IEEE Std 802.1Q header ± transmission

The IEEE Std 802.1Q header is carried within the frame to the transmitting MAC port, where the decision to strip out the header before transmission is made, based on the port configuration. If the port is configured as an access port, the tag is stripped before transmission. If the frame is only 64 bytes long, four bytes of pad (0s) are inserted between the end of the data and the start of the CRC word (a new CRC value is calculated and inserted in the frame). Three, two, and one byte(s) are inserted for 65-, 66-, and 67-byte frames, respectively. If the port is configured as a nonaccess port, the VID is compared with the default port VID. If they match, the header is stripped; otherwise, the header is retained.

If the frame is transmitted to the NM port, no header stripping occurs; the frame is transmitted unaltered. It may contain one or two IEEE Std 802.1Q headers, depending on how the frame is received.

address maintenance

The addresses within the IALE can be maintained automatically by the TNETX4090, where addresses are learned/updated from the wire and deleted using one of two aging algorithms looked up during frame-routing determination. Multicast addresses are not automatically learned or aged. The attached CPU can add/update, find, or delete address records (see TNETX4090 Programmer's Reference Guide, literature number SPAU003, for details) via the DIO interface.

The learning and aging processes are completely independent. This allows addresses to be automatically learned from the wire, but allows the CPU to manage the aging process under software control.

spanning-tree support

Each port provides independent controls to block reception or transmission of frames, learning of addresses, or disable the port on a per-port basis. Blocking can be overridden to allow reception or transmission of spanning-tree frames.

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Contents Description MAC MII MIIMAC Eeprom CPU I/F DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted AlphabeticallyReset Sdma SAD0 Jtag interface Terminal FunctionsControl logic interface Terminal Internal Description Name RESISTOR²M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii modeTerminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SwitchMII management interface Rdram interface Eeprom interface DIO interfaceLED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNETVLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports 0x90Ex Port no Head Statistic TailSignal Description DMA Interface SignalsAddress-Lookup Statistics Receiving/transmitting management framesDIO Interface During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portFCS Vlan IDTpid TCI CRCTNETX4090 Full-duplex NM port PHY management interfaceNM bandwidth and priority Interrupt processingMAC interface Interframe gap enforcement Adaptive performance optimization APOBackoff Receive versus transmit prioritySpeed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Pause Negotiation in MII Mode Port 8 Duplex Negotiation in MII ModeFull-duplex hardware flow control OutcomePretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN Pretag on reception Transmit Pretag Bit DefinitionsLearning Format Receive Pretag Bit Definitions BIT Name FunctionRing-cascade topology Directed Format Receive Pretag Bit DefinitionsRXD Flow COL TXD TNETX4090 RXD Flow COL TXDRing-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Port LED States Compatibility with future device revisionsCollision LED States State DisplayLED Status Bit Definitions and Shift Order PCS duplex LEDLamp test Multi-LED displayBUS Enable GND Rdram BUS Ctrl SIN BUS Enable GND BUS Ctrl Rdram SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDDHighz instruction Jtag Instruction OpcodesRacbist instruction Jtag Bist StatusVlan support Frame routingIale Ieee Std 802.1Q tags ± reception Address maintenanceIeee Std 802.1Q header ± transmission Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharingTrunk Group 0 Port Membership Trunk0Ports Register Port trunking exampleTrunk Group 1 Port Membership Trunk1Ports Register Extended port awarenessFlow control Hardware flow control Other flow-control mechanismsMulticast limit System test capabilitiesInternal wrap test Reading RdramPHY TNETX4090 Duplex wrap testMIN NOM MAX Unit Recommended operating conditionsReset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions PMA receive see Figure Physical medium attachment interface port ReceivePMA transmit see Figure TransmitGmii receive see Figure Gmii portGmii transmit see Figure Gmii Clock PMA and Gmii clock see FigureMII receive see Figure MII ports 0±8MII clock see Figure MII transmit see FigureRdram see Figure Rdram interfaceDtxclk Drxclk Dbusctrl DbusenDIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see FigureEeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOL VOHTTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TBD TNETX4090GGP Obsolete BGAImportant Notice
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