Texas Instruments TNETX4090 specifications 100-/1000-Mbit/s PHY interface port

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TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

100-/1000-Mbit/s PHY interface (port 8)

This port is controlled by an IEEE Std 802.3-compliant MAC.

speed, duplex, and flow-control negotiation

When in PMA mode and autonegotiation is enabled, the on-chip PCS layer attempts to establish a compatible mode of operation with the attached serializer/deserializer (SERDES).

If manual override has been established, no autonegotiation takes place and the interface mode of operation is determined by the values in Port8Control.

The PCS layer may be forced to start autonegotiation by writing a 0 and then a 1 to the neg bit in Port8Control, but, alternatively, you could hit the newaneg bit in PCS8Control.

Figure 4 shows how the gigabit port on the TNETX4090 can be connected to a SERDES device. Table 1 gives a description of the device terminals.

M08_TXD0±M08_TXD7

M08_TXEN

M08_TXER

M08_EWRAP

M08_LINK

TNETX4090

Gigabit Port Terminals

M08_RXD0±M08_RXD7

M08_RXDV

M08_RXER

M08_LREF

M08_COL

M08_RCLK

M08_GTCLK

M08_RFCLK

		TD0±TD7
		TD8
		TD9
NC		SYNC
NC		SYNC
VCC		SYNCEN
VCC		SYNCEN
		LOOPEN	DOUT_TXP		Serial Data
Tie to Signal Detect Terminal of			DOUT_TXP		Serial Data
Tie to Signal Detect Terminal of			DOUT_TXN		Output
Optical Receiver, SERDES Device,			DOUT_TXN		Output
Optical Receiver, SERDES Device,
or to VCC		TNETE2201
		(SERDES Device)
		RD0±RD7	DIN_RXP		Serial Data
		RD8	DIN_RXP		Serial Data
		RD8	DIN_RXN		Input
		RD9	DIN_RXN		Input
		RD9
		LCKREFN
		RBC1
		RBC0
		RFCLK

125-MHz Clock

NOTE: The SYNC output from the SERDES device is not used by the TNETX4090. The SYNCEN input on the SERDES device must be tied high (enabled) for proper operation. The M08_LINK terminal on the TNETX4090 must be tied to the signal detect terminal of an attached optical receiver or tied high if a comparable terminal is unavailable.

Figure 4. TNETX4090 Gigabit Port to SERDES Device Connections

36	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 36

Contents Description MII MAC MIIMAC Eeprom CPU I/F DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball NameReset Sdma SAD0 Terminal Functions Jtag interfaceControl logic interface Terminal Internal Description Name RESISTOR²100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 PulldownM00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4MII management interface Rdram interface DIO interface Eeprom interfacePower supply LED interface100-/1000-Mbit/s port PCS LED interface DIO interface description DIO Internal Register Address MapByte DIO Address ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port Statistics TailPort no Head Statistic Even ODD Ports Port no Head Statistic Tail 0x90ExDMA Interface Signals Signal DescriptionAddress-Lookup Statistics Receiving/transmitting management framesState of DIO signal terminals during hardware reset DIO Interface During Hardware ResetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portVlan ID FCSTpid TCI CRCTNETX4090 PHY management interface Full-duplex NM portNM bandwidth and priority Interrupt processingMAC interface Adaptive performance optimization APO Interframe gap enforcementBackoff Receive versus transmit priority10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Duplex Negotiation in MII Mode Port 8 Pause Negotiation in MII ModeFull-duplex hardware flow control OutcomePretagging and extended port awareness Pretag on transmissionM08GTCLK M08TXEN Transmit Pretag Bit Definitions Pretag on receptionLearning Format Receive Pretag Bit Definitions BIT Name FunctionDirected Format Receive Pretag Bit Definitions Ring-cascade topologyRXD Flow COL TXD TNETX4090 RXD Flow COL TXDSwitch Terminal Ring-Topology ConnectivityM08GTCLK M08TXEN M08RXDV SCL SDA Edio TNETX4090 EclkGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Compatibility with future device revisions Port LED StatesCollision LED States State DisplayPCS duplex LED LED Status Bit Definitions and Shift OrderLamp test Multi-LED displayBUS Enable GND BUS Ctrl Rdram SIN BUS Enable GND Rdram BUS Ctrl SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDDJtag Instruction Opcodes Highz instructionRacbist instruction Jtag Bist StatusFrame routing Vlan supportIale Address maintenance Ieee Std 802.1Q tags ± receptionIeee Std 802.1Q header ± transmission Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source portPort trunking example Trunk Group 0 Port Membership Trunk0Ports RegisterTrunk Group 1 Port Membership Trunk1Ports Register Extended port awarenessFlow control Other flow-control mechanisms Hardware flow controlMulticast limit System test capabilitiesReading Rdram Internal wrap testDuplex wrap test PHY TNETX4090Recommended operating conditions MIN NOM MAX UnitJtag interface Control signals Reset see FigureTiming requirements over recommended operating conditions Physical medium attachment interface port Receive PMA receive see FigureTransmit PMA transmit see FigureGmii port Gmii receive see FigureGmii transmit see Figure PMA and Gmii clock see Figure Gmii ClockMII ports 0±8 MII receive see FigureMII transmit see Figure MII clock see FigureRdram interface Rdram see FigureDtxclk Drxclk Dbusctrl DbusenDIO interface DIO and DMA writes see FigureSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 SrdyEeprom interface Eeprom writes see FigureEeprom reads see Figure LED interface LED see FigureLedclk Leddata VOH VOLTTL Output Macro Propagation-Delay-Time Voltage Waveforms VDD VOH 50% LvcmosVOL VDD Mechanical Data TNETX4090GGP Obsolete BGA TBDImportant Notice