Texas Instruments TNETX4090 specifications DIO and DMA reads see Figure

Page 70

TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

DIO and DMA reads (see Figure 26)

NO.

MIN

MAX

UNIT

1

tw(SCSL)

Pulse duration,

low

2tc

ns

SCS

2

tsu(SRNW)

Setup time, SRNW valid before

↓

0

ns

SCS

3

tsu(SAD)

Setup time, SAD1±SAD0,

valid before

↓

0

ns

SDMA

SCS

4

th(SRNW)

Hold time, SRNW low after

↓

0

ns

SRDY

5

th(SAD)

Hold time, SAD1±SAD0,

valid after

↓

0

ns

SDMA

SRDY

6

th(SCSL)

Hold time,

low after

↓

0

ns

SCS

SRDY

7

tsu(SDATAD)

Setup time from

↓ to SDATA7±SDATA0 driven

0

ns

SRDY

8

td(SRDYZH)

Delay time from

↓ to

↑

10

ns

SCS

SRDY

9

td(SRDYHL)

Delay time from

↓ to

↓

0

²

ns

SCS

SRDY

10

td(SDATAZ)

Delay time from

↑ to SDATA7±SDATA0 3-state

0

10

ns

SCS

11

td(SRDYLH)

Delay time from

↑ to

↑

tc

2tc+10

ns

SCS

SRDY

12

th(SCSH)

Hold time,

high after

↑

0

ns

SCS

SRDY

13

tw(SRDY)

Pulse duration,

high

tc

ns

SRDY

²When the switch is performing certain internal operations (e.g., EEPROM load), there is a delay of up to 20 ms (24C02) or 800 ms (24C08) between SCS being asserted and SRDY being asserted.

		1
3	9		11
2	8	6	10	12

SCS

4

SRNW

5

SAD1±SAD0

SDMA

7

SDATA7±

SDATA0

13

SRDY

Figure 26. DIO and DMA Reads

70	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 70

Contents Description MAC Eeprom CPU I/F MIIMAC MII DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball NameReset Sdma SAD0 Control logic interface Terminal FunctionsJtag interface Terminal Internal Description Name RESISTOR²100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 PulldownM00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4MII management interface Rdram interface DIO interface Eeprom interfaceLED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports Port no Head Statistic Tail 0x90ExAddress-Lookup Statistics DMA Interface SignalsSignal Description Receiving/transmitting management framesDIO Interface State During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portTpid TCI Vlan IDFCS CRCTNETX4090 NM bandwidth and priority PHY management interfaceFull-duplex NM port Interrupt processingMAC interface Backoff Adaptive performance optimization APOInterframe gap enforcement Receive versus transmit priority10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Full-duplex hardware flow control Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode OutcomePretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN Learning Format Receive Pretag Bit Definitions Transmit Pretag Bit DefinitionsPretag on reception BIT Name FunctionRXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology TNETX4090 RXD Flow COL TXDRing-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Collision LED States Compatibility with future device revisionsPort LED States State DisplayLamp test PCS duplex LEDLED Status Bit Definitions and Shift Order Multi-LED displayTNETX4090 VCC NC Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN Sout SCHAIN0 Txclk Vref Rxclk VDDRacbist instruction Jtag Instruction OpcodesHighz instruction Jtag Bist StatusVlan support Frame routingIale Ieee Std 802.1Q header ± transmission Address maintenanceIeee Std 802.1Q tags ± reception Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source portTrunk Group 1 Port Membership Trunk1Ports Register Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Extended port awarenessFlow control Multicast limit Other flow-control mechanismsHardware flow control System test capabilitiesReading Rdram Internal wrap testDuplex wrap test PHY TNETX4090Recommended operating conditions MIN NOM MAX UnitReset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions Physical medium attachment interface port Receive PMA receive see FigureTransmit PMA transmit see FigureGmii receive see Figure Gmii portGmii transmit see Figure PMA and Gmii clock see Figure Gmii ClockMII ports 0±8 MII receive see FigureMII transmit see Figure MII clock see FigureDtxclk Drxclk Rdram interfaceRdram see Figure Dbusctrl DbusenDIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 SrdyEeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOH VOLTTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TNETX4090GGP Obsolete BGA TBDImportant Notice