Motorola 24-Bit Digital Signal Processor manuals

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MOTOROLA TECHNICAL DATA
SEMICONDUCTOR
Addendum to
24-bit Digital Signal Processor Family Manual
3 DSP56K Family
- 6 TABLE OF CONTENTS
- 10 LIST of FIGURES
  - 12 List of Figures (Continued)
- 13 LIST of TABLES
  - Table Page
  - 14 List of Tables (Continued) Table Page
  - 24
  - MAC
    - 31 ADDRESS BUSES
    - 2- 4 DSP56K CENTRAL ARCHITECTURE OVERVIEW
    - Figure 2-1 DSP56K Block Diagram
    - 2.3 ADDRESS BUSES
    - 24-Bit 56K
    - 37 OVERVIEW AND DATA ALU ARCHITECTURE
    - 3 - 4 DATA ARITHMETIC LOGIC UNIT
    - Figure 3-1 DSP56K Block Diagram
    - 24 Bit 56K
    - 40+
      - 48 DATA REPRESENTATION AND ROUNDING
      - Figure 3-10 Convergent Rounding
      - DATA ARITHMETIC LOGIC UNIT 3 - 15
    - 49
    - CAUTION:
      - 57 AGU ARCHITECTURE
      - 4 - 4 ADDRESS GENERATION UNIT
      - Figure 4-1 DSP56K Block Diagram
      - 4.2.2 Offset Register Files (Nn)
      - 24-Bit 56K
    - 70
    - - 71ADDRESSING
      - Table 4-2 Address Modifier Summary
      - 4 - 18 ADDRESS GENERATION UNIT MOTOROLA
      - 79ADDRESSING
      - Figure 4-15 Address Modifier Summary
      - 4 - 26 ADDRESS GENERATION UNIT MOTOROLA
      - 83 OVERVIEW
      - 5 - 4 PROGRAM CONTROL UNIT
      - Figure 5-2 DSP56K Block Diagram
      - 24-Bit 56K Mod-
      - 86 PROGRAM CONTROL UNIT (PCU) ARCHITECTURE
      - Figure 5-3 Three-Stage Pipeline
      - PROGRAM CONTROL UNIT 5 - 7
    - 93*
      - 113 INSTRUCTION FORMATS
      - Figure 6-7 Special Addressing Immediate Data
      - 6 - 16 INSTRUCTION SET INTRODUCTION MOTOROLA
      - when used to address program memory. This addressing mode is classified as a program reference.
      - 115INSTRUCTION FORMATS
      - 6 - 18 INSTRUCTION SET INTRODUCTION MOTOROLA
    - 116 Arithmetic Bit Manipulation Move
      - 117INSTRUCTION GROUPS
      - 6 - 20 INSTRUCTION SET INTRODUCTION MOTOROLA Figure 6-11 Special Addressing Absolute Short Address
      - 119INSTRUCTION GROUPS
      - 6 - 22 INSTRUCTION SET INTRODUCTION MOTOROLA
      - Table 6-1 Addressing Modes Summary
    - 139
    - CAUTION
      - 140
      - Figure 7-1 Fast and Long Interrupt Examples
        RECOGNIZED
      - (b) DSP56K Long Interrupt
      - and their IPLs are listed in Table 7-6. For information on on-chip peripheral interrupt pri-
      - PROCESSING STATES 7 - 13
      - (a) DSP56K Fast Interrupt
        FAST INTERRUPT SERVICE ROUTINE
        LONG INTERRUPT SERVICE ROUTINE
    - 145 CAUTION
      - 1477 - 20 PROCESSING STATES MOTOROLA
      - Figure 7-5 Illegal Instruction Interrupt Serviced by a Long Interrupt
      - 150MOTOROLA PROCESSING STATES 7 - 23
      - Figure 7-7 Trace Exception
      - 154MOTOROLA PROCESSING STATES 7 - 27
      - Figure 7-8 Fast Interrupt Service Routine
      - 1557 - 28 PROCESSING STATES MOTOROLA
        i = INTERRUPT ii = INTERRUPT INSTRUCTION WORD n = NORMAL INSTRUCTION WORD
      - Figure 7-9 Two Consecutive Fast Interrupts
      - 1577 - 30 PROCESSING STATES MOTOROLA
      - Figure 7-10 Long Interrupt Service Routine
      - 158MOTOROLA PROCESSING STATES 7 - 31
      - Figure 7-11 JSR First Instruction of a Fast Interrupt
      - 1597 - 32 PROCESSING STATES MOTOROLA
      - Figure 7-12 JSR Second Instruction of a Fast Interrupt
      - 161RESET PROCESSING STATE
      - Figure 7-13 Interrupting an REP Instruction
      - 7 - 34 PROCESSING STATES MOTOROLA
      - 162RESET PROCESSING STATE
      - MOTOROLA PROCESSING STATES 7 - 35
        i = INTERRUPT ii = INTERRUPT INSTRUCTION WORD n = NORMAL INSTRUCTION WORD i% = INTERRUPT REJECTED
      - Figure 7-14 Interrupting Sequential REP Instructions
      - 175 PORT A INTERFACE
      - 8 - 4 PORT A
      - Figure 8-1 Port A Signals
      - signals (A0-A15), data bus signals (D0-D15), and bus control. The bus control signals can
180
- 183 PLL COMPONENTS
- 9 - 4 PLL CLOCK OSCILLATOR
- Figure 9-2 DSP56K Block Diagram
- 9.2.1 Phase Detector and Charge Pump Loop Filter
- 24-Bit 56K Mod-
- 18501267891011 345 121314181920212223 151617
- 205..
- SECTION 11 ADDITIONAL SUPPORT
  - Dr. BuB Electronic Bulletin Board
222
ola
Motorola DSP
- 225
- SECTION 12
  - Dr. BuB Electronic Bulletin Board
- ADDITIONAL SUPPORT
246
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Motorola DSP
- INSTRUCTION SET DETAILS A - 1
- 270
- APPENDIX A INSTRUCTION SET DETAILS
  - Bit Field Manipulation
  - Loop
  - Move
  - Arithmetic
  - Logical
  - Program Control
  - 276
    - 281 ADDRESSING MODES
    - A - 12 INSTRUCTION SET DETAILS
    - Table A-3 DSP56K Addressing Mode Encoding
    - 283 ADDRESSING MODES
    - A - 14 INSTRUCTION SET DETAILS
    - Table A-4 Addressing Mode Modifier Summary
    - 288CONDITION CODE COMPUTATION
    - The following notes apply to Table A-5:
    - MOTOROLA INSTRUCTION SET DETAILS A - 19
    - Table A-5 Condition Code Computations for Instructions (No Parallel Move)
- 292ABS
- 294ADC
- 296ADD Add ADD
- 298ADDL
- 300ADDR
- 302AND
- 304ANDI
- 306ASL
- 308ASR
- 336BTST
- 340CLR
- 342CMP Compare CMP
- 344CMPM
- 345DEBUG
- 348DEBUGcc
- 350DEC
  - 363
- 368ENDDO
- 370EOR
- 372ILLEGAL
- 374INC
- 386JMP Jump JMP
  - 388+
- 406JSR
- 414LSL
- 416LSR
- 418LUA
- 442U
  - 497 (S1 2-n)D (no parallel move) MPY (
- 506NEG
- 508NOP
- 510NORM
- 512NOT
- 514OR
- 516ORI
  - 521
- 526RESET
- 532ROL
- 534ROR
- 536RTI
- 538RTS
- 544STOP
- 546SUB Subtract SUB
- 548SUBL
- 550SUBR
- 552SWI
- 558TFR
- 560TST
- 562WAIT
  - 566
  - B - 4 BENCHMARK PROGRAMS
  - Table B-1 27-MHz Benchmark Results for the DSP56001R27
  - 568
  - B - 6 BENCHMARK PROGRAMS
  - Figure B-1 20-Tap FIR Filter Example (Sheet 1 of 2)
  - 570
  - B - 8 BENCHMARK PROGRAMS
  - Figure B-1 20-Tap FIR Filter Example (Sheet 2 of 2)
  - 572
  - B - 10 BENCHMARK PROGRAMS
  - Figure B-2 Radix 2, In-Place, Decimation-In-Time FFT (Sheet 1 of 2)
  - 574
  - B - 12 BENCHMARK PROGRAMS
  - Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 1 of 8)
  - Figure B-2 Radix 2, In-Place, Decimation-In-Time FFT (Sheet 2 of 2)
  - 576
  - B - 14 BENCHMARK PROGRAMS
  - Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 3 of 8)
  - Figure B 3 8 Pole 4 Multiply Cascaded Canonic IIR Filter (Sheet 1 of 2)
  - 578
  - B - 16 BENCHMARK PROGRAMS
  - Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 5 of 8)
  - 580
  - B - 18 BENCHMARK PROGRAMS
  - Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 7 of 8)
  - 581
  - Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 8 of 8)
  - BENCHMARK PROGRAMS B - 19
  - 582
  - B - 20 BENCHMARK PROGRAMS
  - 583
  - BENCHMARK PROGRAMS B - 21
  - 584
  - B - 22 BENCHMARK PROGRAMS
  - 585
  - BENCHMARK PROGRAMS B - 23
  - 586
  - B - 24 BENCHMARK PROGRAMS
  - 587
  - BENCHMARK PROGRAMS B - 25
  - 591 INDEX
    - C
    - B
    - A
    - INDEX - 1
    - 592
    - INDEX - 2
    - G
    - F
    - E
    - D
    - 593
    - L
    - J
    - I
    - H
    - INDEX - 3
    - 594
    - INDEX - 4
    - P
    - N
    - M
    - O
    - 595
    - R
    - INDEX - 5