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Limited and Restricted Rights Legend
Contact Address
Contents
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List of Tables
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List of Figures
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About this Manual
Overview of Contents
Abbreviations
This document uses the following abbreviations:
Conventions
The following table describes the conventions used throughout this manual.
Summary of Changes
This manual has been revised and replaces all prior editions.
Comments and Suggestions
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Safety Notes
EMC
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Operation
Installation
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Rear Transition Module
Environment
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Sicherheitshinweise
EMV
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Betrieb
Installation
Rear Transition Module
Umweltschutz
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Introduction
1.1 Features
1.2 Standard Compliances
The CPCI-6020 is designed to be CE compliant and to meet the following standard requirements.
Table 1-1 Features (continued)
Table 1-2 Board Standard Compliances
1.3 Ordering Information
1.3.1 Supported Board Models
Table 1-2 Board Standard Compliances (continued)
1.3.2 Board Accessories
Hardware Preparation and Installation
2.1 Overview
2.2 Unpacking and Inspecting the Board
Shipment Inspection
To inspect the shipment, perform the following steps:
2.3 Overview of Start-up Procedure
Table 2-1 Startup Overview
2.4 Equipment Required
2.5 Environmental and Power Requirements
2.5.1 Environmental Requirements
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2.5.2 Power Requirements
2.5.3 Thermal Requirements
2.6 Hardware Configuration
2.7 CPCI-6020 Baseboard Preparation
2.8 Jumper Settings
2.8.1 Flash Bank Selection
2.8.2 Harrier Power Up Configuration Header
2.8.3 PMC 66 MHz Disable
2.8.4 Enable/Disable +12 V and -12 V Use
2.8.5 Enable/Disable Lockdown of One or More Flash Blocks for Bank A
2.8.6 Enable Write-Protect for Entire Flash on Bank A
2.9 Hardware Installation
2.10 PMC Module Installation
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2.11 CompactFlash Memory Card Installation
2.12 Before You Install or Remove a Board
2.12.1 Watch for Bent Pins or Other Damage
2.12.2 Use Caution When Installing or Removing Boards
2.12.3 Understanding Hot Swap
2.12.4 Recognize Different Injector/Ejector Lever Types
2.12.5 Verify Slot Usage
2.12.6 Preserve EMI Compliance
2.13 Installing and Removing a Module
Installation Procedure
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2.14 Startup and Operation
2.15 System Considerations
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Controls, LEDs, and Connectors
3.3 Front Panel Connectors and LEDs
3.3.1 Front Panel Ethernet Port
3.3.2 Front Panel Asynchronous Serial Port
3.3.3 Front Panel USB ports
3.3.4 ABORT# Switch
3.3.5 RESET# Switch
3.3.6 Front Panel LEDs
3.4 Connector Pin Assignments
3.4.1 CompactPCI Bus Connectors
Table 3-7 J2 CompactPCI Connector
Table 3-7 J2 CompactPCI Connector (continued)
3.4.2 CompactPCI User I/O Connector
3.4.3 CompactPCI User I/O Connector
3.4.4 CompactPCI User I/O Connector
Table 3-12 J5 Signal Descriptions
Table 3-12 J5 Signal Descriptions (continued)
3.4.5 Memory Mezzanine Connectors
Table 3-12 J5 Signal Descriptions (continued)
Table 3-13 J8 and J27 Memory Mezzanine Connector
3.4.6 PCI Mezzanine Card (PMC) Connectors
Table 3-13 J8 and J27 Memory Mezzanine Connector (continued)
Table 3-14 PMC Connector J11 Pin Assignments
The following table shows the pin assignments for J12.
Table 3-15 J12 PMC Connector J12 Pin Assignments
Table 3-14 PMC Connector J11 Pin Assignments (continued)
Table 3-16 shows the J13 pin assignments:
Table 3-16 PMC Connector J13 Pin Assignments
Table 3-15 J12 PMC Connector J12 Pin Assignments (continued)
The following table shows the J14 pin assignments.
Table 3-17 PMC Connector J14 Pin Assignments
Table 3-16 PMC Connector J13 Pin Assignments (continued)
3.4.7 Lock Down Flash Enable Jumper
Table 3-17 PMC Connector J14 Pin Assignments (continued)
Table 3-18 J17 Lock Down Flash Enable Jumper
3.4.8 PMC 66 Mhz Disable Jumper
3.4.9 Remote Switch Connector
3.4.10 Flash Write Protect Enable Jumper
3.4.11 Harrier Power Up Configuration
3.4.12 Xport Flash Bank Select Header
3.4.13 RISCWatch Header
3.4.14 Mictor Debug Connector
Table 3-24 J25 RISCWatch Header Pin Assignments (continued)
Table 3-25 J28 Debug Connector
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Functional Description
4.1 Overview
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4.3 Local PCI Bus Resources
4.3.1 PCI Bus A Resources
4.3.1.1 Local CompactPCI Bus
4.3.1.2 Remote (Expansion) CompactPCI Bus
4.3.1.3 Primary Ethernet Channel
4.3.1.4 ISA Bridge, Including EIDE Function
4.3.1.5 EIDE Interface
4.3.1.6 ISA Bus Resources
4.3.1.7 Synchronous Serial Ports
4.4 PCI Bus B Resources
4.4.1 PMC Slot
4.4.2 Secondary Ethernet Channel
4.5 Processor Bus Resources
4.5.1 Processor
4.5.2 L2 Cache
4.6 Harrier System Memory Controller and PCI Host Bridge ASIC
4.6.1 Dual Harrier Assignments
4.6.2 Harrier Power-Up Configuration
Table 4-2 Harrier Power-Up Configuration Settings (continued)
4.6.3 Debug Connector
4.6.4 PPC Bus Arbitration
4.7 ECC Memory Bus Resources
4.7.1 Harrier A Memory Bus
4.7.2 Harrier B Memory Bus
4.7.3 RAM500 Memory Mezzanine
4.8 Harrier Xport Resources
4.8.1 Harrier A, Channel 0 - Onboard Bank A Flash
4.8.2 Harrier A, Channel 1 - Socketed Bank B Flash
4.8.3 Harrier A, Channel 2 - NVRAM, RTC, External Register Set
4.8.4 Harrier A, Channel 3
4.8.5 Harrier B, Channel 0, 1, 2 and 3
4.9 Other Harrier Resources
4.9.1 I2C Bus Resources - Serial EEPROM
4.9.2 Asynchronous Serial Ports
4.9.3 32-Bit Timers
4.9.4 Watchdog Timers
4.10 Other Board Resources
4.10.1 Miscellaneous Control and Status
4.10.2 Clock Generator
4.10.3 Onboard Power Supplies
4.10.4 Board Reset Logic
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4.10.5 Soft Reset
4.10.6 Front Panel Resources
4.10.7 ABORT# and RESET# Switches
4.10.8 On-Board LEDs
4.10.9 Harrier Power Up Configuration Header
4.11 Hot Swap Support
4.12 High Availability Support
4.12.1 HSC Bridge Board Interface
4.12.2 Local CompactPCI Bus Interface
4.12.3 Secondary Bus Arbitration
4.12.4 Secondary Bus Tri-Stating
4.12.5 System Slot Hot Swap
4.13 EIDE Interface
4.14 Ethernet Interface
4.15 Hot Swap Support
4.16 PMC Interface Module (PIM)
4.17 Asynchronous Serial Ports
4.18 Synchronous Serial Ports
4.19 I/O Signal Multiplexing (IOMUX)
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4.20 Serial Interface Modules (SIM)
4.21 PMC Interface Module (PIM)
4.22 PMC Interface Module Form Factor
4.23 PMC Interface Connector
4.24 Host I/O Connector
4.25 Speaker Port
4.26 Floppy Disk Port
4.27 Mouse and Keyboard Port
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Firmware
5.1 PPCBug Overview
5.2 PPCBug Basics
5.3 Memory Requirements
5.4 PPCBug Implementation
5.5 MPU, Hardware and Firmware Initialization
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5.6 Using PPCBug
5.7 Debugger Commands
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Table 5-1 Debugger Commands (continued)
5.8 Diagnostic Tests
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RAM500 Memory Expansion Module
6.1 Overview
6.2 RAM500 Description
6.3 RAM500 Module Installation
6.4 Features
6.4.1 SROM
6.4.2 Host Clock Logic
6.4.3 Serial Presence Detect (SPD) Data
6.5 RAM500 Connectors
6.5.1 Bottom Side Memory Expansion Connector (P1)
Table 6-3 RAM500 Bottom Side Connector (P1) Pin Assignments (continued)
Table 6-3 RAM500 Bottom Side Connector (P1) Pin Assignments (continued)
6.5.2 Top Side Memory Expansion Connector (J1)
Table 6-4 RAM500 Top Side Connector (J1) Pin Assignments (continued)
6.6 RAM500 Programming Issues
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Transition Module Preparation and Installation
7.1 Overview
7.2 General Description
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Component Layout Transition Module Preparation and Installation
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C) 129
7.2.1 Component Layout
7.2.2 Rear Panel Connectors
7.3 Unpacking and Inspecting the RTM
7.4 Preparing the Transition Module
7.4.1 Serial Ports 1 and 2
7.4.2 Serial Ports 3 and 4
7.4.3 Serial Interface Module Circuitry
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Port Configuration Transition Module Preparation and Installation
CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C) 135
7.4.4 Port Configuration
CPCI-6020
Transition Module Preparation and Installation Installing the SIMs
136
7.5 Installing the SIMs
Figure 7-6 EIA-232-D DTE Ports 3 and 4 Configuration
CPCI-6020
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7.6 Installing the PIM
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7.7 Installing and Removing the Transition Module
Removal Procedure
7.8 Connectors and Cables
Table 7-3 Rear Transition Module Cables
Table 7-2 Rear Transition Module Connectors/Headers (continued)
7.9 Connector Pin Assignments
7.9.1 CompactPCI Connectors
7.9.2 PMC I/O Module Connector
Table 7-5 PMC I/O Module - PMC I/O Connector Pin Assignments
Table 7-4 PMC I/O Module - Host I/O Connector Pin Assignments (continued)
Table 7-5 PMC I/O Module - PMC I/O Connector Pin Assignments (continued)
7.9.3 10BaseT/100BaseTx Connectors
7.9.4 COM1 Connector
7.9.5 COM2 Header
7.9.6 EIDE Header
7.9.7 Floppy Port Header
7.9.8 +5VDC Power Connector
7.9.9 Keyboard/Mouse Connector
7.9.10 Sync/Async Serial Ports
7.9.11 Speaker Output Header
Table 7-13 Sync/Async Serial Connector Pin Assignments (continued)
Table 7-14 Speaker Output Connector Pin Assignments
CNFG and ENV Commands
8.1 Overview
8.2 CNFG - Configure Board Information
8.3 ENV - Set Environment
8.4 Configuring the PPCBug Parameters
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A
A.1 Embedded Communications Computing Documents
A.2 Manufacturers Documents
A.3 Related Specifications
Table A-2 Manufacturers Documents (continued)
Table A-3 Related Specifications
Table A-3 Related Specifications (continued)
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Index
Symbols
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