Motorola CPCI-6020 manual Processor Bus Resources, 2 L2 Cache

Processor Bus Resources Functional Description

4.5Processor Bus Resources

Devices resident on the processor bus of the CPCI-6020 are a single processor, two Harriers (denoted Harrier A and Harrier B) and a Mictor debug connector. The bus is the standard 60x interface running at 100 MHz. Processor address and data bus parity generation and checking is supported in conjunction with the Harrier ASICs. The MPX Bus extension, which the MCP7410 is capable of, is not supported.

The MCP7410 processor uses a +2.5 V signalling level and is not +3.3 V tolerant. Care should be taken that probe boards attached to the Mictor debug connector do not pull up or drive signals in violation of this. The JTAG port is tolerant of +3.3 V signals.

4.5.1Processor

The CPCI-6020 has the 360-pin CBGA foot print that supports the MPC7410 family of processors. The CPCI-6020 supports an external processor bus speed of 100 MHz. The common processor configuration will support variable core voltages between 0.8V and +3.3 V and I/O voltages of either +2.5 V or +3.3 V.

4.5.2L2 Cache

The CPCI-6020 uses a back-side L2 cache structure via the MPC7410 processor chip families. The L2 cache is implemented with an on-chip, 2-way set-associative tag memory and external direct-mapped synchronous SRAMs for data storage. The external SRAMs are accessed through a dedicated 72-bit wide (64 bits of data and 8 bits of parity) L2 cache port. The MPC7410 processor can support up to 2 MB. The L2 cache can operate in copyback or write- through modes and supports system cache coherency through snooping. Data parity generation and checking can be disabled by programming the processor L2 cache control registers accordingly. The MPC7410 processor also supports direct mapping of the SRAM memory, in conjunction with normal L2 cache operation. In this mode, a portion of the SRAM memory space may be mapped to appear as a private memory space in the memory map. Refer to the processor data sheet for additional information.

The L2 cache data SRAM for the CPCI-6020 is implemented using two 128 KB x 36-bit or 256 KB x 36-bit synchronous pipelined burst SRAMs providing a total 2 MB of L2 cache. Either memory size is able to support a minimum L2 bus speed of 200 MHz. The common SRAM footprint supports only+ 3.3 V core voltages and either +2.5 V or +3.3 V I/O voltages.

4.6Harrier System Memory Controller and PCI Host Bridge ASIC

The Harrier ASIC provides the bridge function between the PPC60X Bus, the system memory and the PCI Local Bus. The Harrier ASIC provides the following key features:

z100 MHz PowerPC Bus interface

zSDRAM interface supporting up to eight banks of 256 MB each, with ECC

z32/64-bit Rev 2.1 compliant PCI Bus interface capable of running up to 66 MHz

CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C) 87