Motorola CPCI-6020 Other Harrier Resources, 1 I2C Bus Resources Serial Eeprom, 3 32-Bit Timers

Other Harrier Resources Functional Description

4.9Other Harrier Resources

The following subsections discussion other resources that are available through the Harrier ASIC.

4.9.1I2C Bus Resources - Serial EEPROM

The CPCI-6020 contains two 8 KB Serial EEPROM devices onboard and provisions for four 256-byte Serial EEPROM devices on memory mezzanines.

zOne 8 KB Serial EEPROM provides for Vital Product Data (VPD) storage of the module hardware configuration

zOne 8 KB device for storage of user configuration data.

The contents of the 8 KB devices are accessed by providing a two-byte address with the same device ID, instead of the standard one-byte address as used in the 256-byte devices. The 256- byte devices provide for Serial Presence Detect (SPD) memory configuration information. The Serial EEPROMs for VPD, user data and memory attached to Harrier A are accessed through I2C port 0 in the Harrier A ASIC.

The Serial EEPROM’s for memory attached to Harrier B are accessed through I2C port 0 in the Harrier B ASIC. Refer to the CPCI-6020 CompactPCI Single Board Computer Programmer’s Reference Guide for SROM device address assignments.

4.9.2Asynchronous Serial Ports

The CPCI-6020 provides two asynchronous serial interfaces. UART0 and UART1 in the Harrier A provide the 16550 compatible UART controllers. The UART0 port signals are wired to an RS- 232 transceiver which interfaces to the front panel RJ-45 connector. The UART0 port may optionally be wired to the backplane via J5 instead. The UART1 port is wired to the J5 connector only. An onboard 1.8432 MHz oscillator provides the baud rate clock for the UARTs. Refer to the Harrier Application Specific Integrated Circuit Programmer’s Reference Guide for additional UART information.

4.9.332-Bit Timers

Four 32-bit timers are provided by each Harrier (MPIC) that may be used for system timing or to generate periodic interrupts. Each timer is driven by a divide-by-eight prescaler which is synchronized to the PPC processor clock. For a 100 MHz processor bus, the timer frequency would be 12.5 MHz. Refer to the Harrier Engineering Specification for additional information and programming details on these timers.

4.9.4Watchdog Timers

Both Harrier ASICs contains two Watchdog Timers, WDT1 and WDT2. Each timer is functionally equivalent but independent. These timers will continuously decrement until they reach a count of 0 or are reloaded by software. The time-out period is programmable from 1 microsecond up to 32 minutes. If the timer count reaches 0, a timer output signal will be

CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C) 93