AMD Am188TMER List of Tables, Processor Release Level PRL Register High-Order Byte Values

LIST OF TABLES

Table 2-1	Instruction Set			. . 2-5
Table 2-2	Segment Register Selection Rules			. . 2-8
Table 2-3	Memory Addressing Mode Examples			. 2-10
Table 3-1	PIO Pin Assignments—Numeric Listing			3-10
Table 3-2	PIO Pin Assignments—Alphabetic Listing			3-11
Table 3-3	Bus Cycle Encoding			. 3-13
Table 3-4	Clocking Modes			. 3-16
Table 3-5	Maximum and Minimum Clock Frequencies			. 3-23
Table 4-1	Processor Release Level (PRL) Register High-Order Byte Values			. . 4-6
Table 4-2	Initial Register State After Reset			. . 4-9
Table 5-1	Chip Select Register Summary			. . 5-1
Table 5-2	UMCS Block Size Programming Values			. . 5-4
Table 5-3	LMCS Block Size Programming Values			. . 5-6
Table 5-4		Block Size Programming		5-10
	MCS
Table 5-5	PCS		Address Ranges	. 5-13
Table 5-6				5-13
	PCS3–PCS0 Wait-State Encoding
Table 8-1	Am186ER and Am188ER Microcontroller Interrupt Types			. . 8-3
Table 8-2	Interrupt Controller Registers in Master Mode			. 8-13
Table 8-3	Priority Level			. 8-15
Table 8-4	Priority Field Mask (Master Mode)			. 8-24
Table 8-5	Interrupt Controller Registers in Slave Mode			. 8-29
Table 8-6	Priority Field Mask (Slave Mode)			. 8-34
Table 9-1	Timer Control Unit Register Summary			. . 9-1
Table 10-1	DMA Controller Register Summary			. 10-1
Table 10-2	Synchronization Type			. 10-4
Table 10-3	Maximum DMA Transfer Rates			10-10
Table 11-1	Asynchronous Serial Port Register Summary			. 11-1
Table 11-2	Parity Mode Bit Settings			. 11-3
Table 11-3	Serial Port Baud Rate Table			. 11-7
Table 12-1	Synchronous Serial Interface Register Summary			. 12-1
Table 12-2	SCLK Divider Values			. 12-4
Table 13-1	PIO Pin Assignments and Register Bits			. 13-2
Table 13-2	PIO Mode and PIO Direction Settings			. 13-3
Table A-1	Internal Register Summary			. .A-2

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