AMD Am186TMER, Am188TMER user manual Index

DMA 1 Destination Address High Register, 10-6DMA 1 Destination Address Low Register, 10-7DMA 1 Interrupt Control Register

Master mode, 8-18Slave mode, 8-30

DMA 1 Source Address High Register, 10-8DMA 1 Source Address Low Register, 10-9DMA 1 Transfer Count Register, 10-5Documentation, iii, xiv

Double word data type, 2-8

DR/DT bit (Data Receive/Transmit Complete), 12-3DRQ1-DRQ0 signals (DMA Requests), 3-4DSA15-DSA0 field (DMA Source Address Low), 10-9DSA19-DSA16 field (DMA Source Address High), 10-8DT/R signal (Data Transmit or Receive), 3-4

E

E bit (Enable RCU), 7-2Effective address, 2-10Emulators, pins used by, 3-17EN bit (Enable Bit)

Timer 0 Mode/Control Register, 9-3

Timer 1 Mode/Control Register, 9-3

Timer 2 Mode/Control Register, 9-5EN bit (Enable Power-Save Mode), 4-7Enable RCU Register, 7-2End-of-Interrupt (EOI) Register

description, 8-28End-of-interrupt (EOI) Register

programming, 8-12EX bit (Pin Selector), 5-11Example system design, 1-6–1-7Exceptions, instruction, 8-3EXT bit (External Clock Bit)

Timer 0 Mode/Control Register, 9-4

Timer 1 Mode/Control Register, 9-4External clock source, 3-24

External interrupt acknowledge bus cycles table, 8-8Extra Segment (ES) Register, 2-8

F

F2-F0 field (Clock Divisor Select) System Configuration Register, 4-8

FER bit (Framing Error), 11-4Figure

DMA Unit Block Diagram, 10-2

external interrupt acknowledge bus cycles, 8-8Fully nested mode interrupt controller connections,

8-10

Read and write bus timing, 3-19–3-20FLAGS Register, 2-2

Frequency, clock, 3-23FTP site, xiv

Fully nested mode, 8-10

Fully nested mode interrupt controller connections, 8-10Functional system design, 1-6–1-7

FusionE86 catalog, xiv

G

General registers, 2-1

H

HLDA signal (Bus Hold Acknowledge), 3-4HOLD signal (Bus Hold Request), 3-5

I

I/O space, 2-4

I4-I0 field (Interrupt In-Service), 8-23I4-I0 field (Interrupt Mask), 8-25

I4-I0 field (Interrupt Requests), 8-22IF bit (Interrupt-Enable Flag)

Processor Status Flags Register, 2-3IF bit (Interrupt-Enable flag)

programming, 8-2

IMDIS signal (Internal Memory Disable), 3-13Immediate operands, 2-10

Indexed mode addressing, 2-10INH bit (Inhibit Bit)

Timer 0 Mode/Control Register, 9-3

Timer 1 Mode/Control Register, 9-3

Timer 2 Mode/Control Register, 9-5In-Service Register

Master mode, 8-23Slave mode, 8-33Instruction exceptions, 8-3

Instruction set, 2-4INT bit (Interrupt Bit)

Timer 0 Mode/Control Register, 9-3

Timer 1 Mode/Control Register, 9-3

Timer 2 Mode/Control Register, 9-5INT0 Control Register

Master mode, 8-14

INT0 signal (Maskable Interrupt Request 0), 3-5INT1 Control Register

Master mode, 8-14

INT1 signal (Maskable Interrupt Request 1), 3-5INT2 Control Register

I-4 Index