AMD Am186TMER, Am188TMER user manual Chapter DMA Controller, Viii Table of Contents

CHAPTER 10	DMA CONTROLLER
	10.1	Overview	. 10-1
	10.2	DMA Operation	. 10-1
	10.3	Programmable DMA Registers	. 10-2
		10.3.1 DMA Control Registers
		(D0CON, Offset CAh, D1CON, Offset DAh)	. 10-3
		10.3.2 DMA Transfer Count Registers
		(D0TC, Offset C8h, D1TC, Offset D8h)	. 10-5
		10.3.3 DMA Destination Address High Register (High Order Bits)
		(D0DSTH, Offset C6h, D1DSTH, Offset D6h)	. 10-6
		10.3.4 DMA Destination Address Low Register (Low Order Bits)
		(D0DSTL, Offset C4h, D1DSTL, Offset D4h)	. 10-7
		10.3.5 DMA Source Address High Register (High Order Bits)
		(D0SRCH, Offset C2h, D1SRCH, Offset D2h)	. 10-8
		10.3.6 DMA Source Address Low Register (Low Order Bits)
		(D0SRCL, Offset C0h, D1SRCL, Offset D0h)	. 10-9
	10.4 DMA Requests		10-10
		10.4.1 Synchronization Timing	10-11
		10.4.2 DMA Acknowledge	10-12
		10.4.3 DMA Priority	10-12
		10.4.4 DMA Programming	10-12
		10.4.5 DMA Channels on Reset	10-13

CHAPTER 11 ASYNCHRONOUS SERIAL PORT

11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2.1 Serial Port Control Register (SPCT, Offset 80h) . . . . . . . . . . . . . 11-2 11.2.2 Serial Port Status Register (SPSTS, Offset 82h) . . . . . . . . . . . . 11-4 11.2.3 Serial Port Transmit Data Register (SPTD, Offset 84h) . . . . . . . 11-5 11.2.4 Serial Port Receive Data Register (SPRD, Offset 86h). . . . . . . . 11-6 11.2.5 Serial Port Baud Rate Divisor Register (SPBAUD, Offset 88h). . 11-7

CHAPTER 12 SYNCHRONOUS SERIAL INTERFACE

12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.1.1 Four-Pin Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.2 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2.1 Synchronous Serial Status Register (SSS, Offset 10h). . . . . . . . 12-3 12.2.2 Synchronous Serial Control Register (SSC, Offset 12h) . . . . . . . 12-4 12.2.3 Synchronous Serial Transmit 1 Register (SSD1, Offset 14h)

Synchronous Serial Transmit 0 Register (SSD0, Offset 16h) . . . 12-5 12.2.4 Synchronous Serial Receive Register (SSR, Offset 18h) . . . . . . 12-6

12.3 SSI Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7

CHAPTER 13 PROGRAMMABLE I/O PINS

13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2 PIO Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.2.1 PIO Mode 1 Register (PIOMODE1, Offset 76h) . . . . . . . . . . . . . 13-3 13.2.2 PIO Mode 0 Register (PIOMODE0, Offset 70h) . . . . . . . . . . . . . 13-3

13.3 PIO Direction Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3.1 PIO Direction 1 Register (PDIR1, Offset 78h) . . . . . . . . . . . . . . 13-4 13.3.2 PIO Direction 0 Register (PDIR0, Offset 72h) . . . . . . . . . . . . . . 13-4

13.4 PIO Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.4.1 PIO Data Register 1 (PDATA1, Offset 7Ah) . . . . . . . . . . . . . . . . 13-5 13.4.2 PIO Data Register 0 (PDATA0, Offset 74h) . . . . . . . . . . . . . . . . 13-5

13.5 Open-Drain Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

APPENDIX A REGISTER SUMMARY

viii Table of Contents