When the external bus master has finished using the local bus, it

 

 

 

indicates this to the microcontroller by deasserting HOLD. The

 

 

 

microcontroller responds by deasserting HLDA.

 

 

 

If the microcontroller requires access to the bus (e.g., for refresh), it will

 

 

 

deassert HLDA before the external bus master deasserts HOLD. The

 

 

 

external bus master must be able to deassert HOLD and allow the

 

 

 

microcontroller access to the bus.

HOLD

Bus Hold Request (input, synchronous, level-sensitive)

 

 

 

This pin indicates to the microcontroller that an external bus master

 

 

 

needs control of the local bus. For more information, see the HLDA pin

 

 

 

description.

 

 

 

The Am186ER and Am188ER microcontrollers’ HOLD latency time, the

 

 

 

time between HOLD request and HOLD acknowledge, is a function of

 

 

 

the activity occurring in the processor when the HOLD request is

 

 

 

received. A HOLD request is second only to DRAM refresh requests in

 

 

 

priority of activity requests received by the processor. This implies that

 

 

 

if a HOLD request is received just as a DMA transfer begins, the HOLD

 

 

 

latency can be as great as four bus cycles. This occurs if a DMA word

 

 

 

transfer operation is taking place (Am186ER microcontroller only) from

 

 

 

an odd address to an odd address. This is a total of 16 clock cycles or

 

 

 

more if wait states are required. In addition, if locked transfers are

 

 

 

performed, the HOLD latency time is increased by the length of the

 

 

 

locked transfer.

INT0

Maskable Interrupt Request 0 (input, asynchronous)

 

 

 

This pin indicates to the microcontroller that an interrupt request has

 

 

 

occurred. If the INT0 pin is not masked, the microcontroller transfers

 

 

 

program execution to the location specified by the INT0 vector in the

 

 

 

microcontroller interrupt vector table.

 

 

 

Interrupt requests are synchronized internally and can be edge-

 

 

 

triggered or level-triggered. To guarantee the interrupt is recognized,

 

 

 

the device issuing the request must continue asserting INT0 until the

 

 

 

request is acknowledged.

 

 

 

Maskable Interrupt Request 1 (input, asynchronous)

INT1/SELECT

 

 

 

 

Slave Select (input, asynchronous)

 

 

 

INT1—This pin indicates to the microcontroller that an interrupt request

 

 

 

has occurred. If the INT1 pin is not masked, the microcontroller transfers

 

 

 

program execution to the location specified by the INT1 vector in the

 

 

 

microcontroller interrupt vector table.

 

 

 

Interrupt requests are synchronized internally, and can be edge-

 

 

 

triggered or level-triggered. To guarantee the interrupt is recognized,

 

 

 

the device issuing the request must continue asserting INT1 until the

 

 

 

request is acknowledged.

 

 

 

 

—When the microcontroller interrupt control unit is operating

 

 

 

SELECT

 

 

 

as a slave to an external master interrupt controller, this pin indicates

 

 

 

to the microcontroller that an interrupt type appears on the address and

 

 

 

data bus. The INT0 pin must indicate to the microcontroller that an

 

 

 

interrupt has occurred before the

 

pin indicates to the

 

 

 

SELECT

 

 

 

microcontroller that the interrupt type appears on the bus.

System Overview

3-5

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Image 37
AMD Am188TMER Bus Hold Request input, synchronous, level-sensitive, Maskable Interrupt Request 0 input, asynchronous