AMD Am188TMER, Am186TMER user manual Serial Port Baud Rate Divisor Register SPBAUD, Offset 88h

11.2.5Serial Port Baud Rate Divisor Register (SPBAUD, Offset 88h)

This register (Figure 11-5) specifies a clock divisor for the generation of the serial clock that controls the serial port. The serial clock rate is 16 times the baud rate of transmission or reception of data. The SPBAUD register specifies the number of internal processor cycles in one phase (half period) of the 16x serial clock.

If power-save mode is in effect, the baud rate divisor must be reprogrammed to reflect the new processor clock frequency.

A general formula for the baud rate divisor is: BAUDDIV=(Processor Frequency¸(32 × Baud Rate))–1

The maximum baud rate is 1/32 of the internal processor clock and is achieved by setting BAUDDIV=0000h. For a 40-MHz clock, a baud rate of 9600 can be achieved with BAUDDIV=129 (81h). A 1% error applies.

Figure 11-5 Serial Port Baud Rate Divisor Register (SPBAUD, offset 88h)

15 7 0

BAUDDIV

The value of SPBAUD at reset is undefined.

Bits 15–0: Baud Rate Divisor (BAUDDIV) —This field specifies the divisor for the internal processor clock that generates one phase (half period) of the serial clock. The serial clock operates at 16 times the data transmission or reception baud rate.

Table 11-3shows baud rate divisors for a range of common baud rates and processor clock rates.

Table 11-3 Serial Port Baud Rate Table

Baud Rate		Divisor Based on CPU Clock Rate
	20 MHz		25 MHz	33 MHz	40 MHz
300	2082		2603	3471	4165
600	1040		1301	1735	2082
1200	519		650	867	1040
2400	259		324	433	519
4800	129		161	216	259
9600	64		80	107	129
14,400	42		53	71	85
19,200	31		39	53	64
625 Kbaud	0		N/A	N/A	1
781.25 Kbaud	N/A		0	N/A	N/A
1.041 Mbaud	N/A		N/A	0	N/A
1.25 Mbaud	N/A		N/A	N/A	0

Asynchronous Serial Port 11-7