Peripheral Chip Selects output, synchronous

executing NMI interrupt service routine. As with all hardware interrupts,

the IF (interrupt flag) is cleared when the processor takes the interrupt,

disabling the maskable interrupt sources. However, if maskable

interrupts are re-enabled by software in the NMI interrupt service routine

(via the STI instruction for example), the fact that an NMI is currently in

service will not have any effect on the priority resolution of maskable

interrupt requests. For this reason, it is strongly advised that the interrupt

service routine for NMI does not enable the maskable interrupts.

An NMI transition from Low to High is latched and synchronized

internally, and it initiates the interrupt at the next instruction boundary.

To guarantee that the interrupt is recognized, the NMI pin must be

asserted for at least one CLKOUTA period. Because NMI is rising edge

sensitive, holding the pin High during reset has no effect on program

execution.

Peripheral Chip Selects (output, synchronous)

PCS3–PCS 0

These pins indicate to the system that a memory access is in progress

to the corresponding region of the peripheral memory block (either I/O

or memory address space). The base address of the peripheral memory

block is programmable.

PCS3–PCS0 are held High during a bus hold

or reset condition.

Unlike the

and LCS chip selects, the

outputs assert with the

UCS

PCS

multiplexed AD address bus.

Note:

is not available on the Am186ER and Am188ER

PCS4

microcontrollers. Note also that each peripheral chip select asserts over

a 256-byte address range, which is twice the address range covered by

peripheral chip selects in the 80C186 and 80C188 microcontrollers.

Peripheral Chip Select 5 (output, synchronous)

PCS5/A1

Latched Address Bit 1 (output, synchronous)

—This pin indicates to the system that a memory access is in

PCS5

progress to the sixth region of the peripheral memory block (either I/O

or memory address space). The base address of the peripheral memory

block is programmable.

is held High during a bus hold or reset

PCS5

condition. It is also held High during reset.

Note: Unlike the

and

chip selects, the

outputs assert

UCS

LCS

PCS

with the multiplexed AD address bus. Note also that each peripheral

chip select asserts over a 256-byte address range, which is twice the

address range covered by peripheral chip selects in the 80C186 and

80C188 microcontrollers.

A1—When the EX bit in the

and

Auxiliary Register is 0, this

MCS

PCS

pin supplies an internally latched address bit 1 to the system. During a

bus hold condition, A1 retains its previously latched value.

Peripheral Chip Select 6 (output, synchronous)

PCS6/A2

Latched Address Bit 2 (output, synchronous)

—This pin indicates to the system that a memory access is in

PCS6

progress to the seventh region of the peripheral memory block (either

I/O or memory address space). The base address of the peripheral

memory block is programmable.

is held High during a bus hold