AMD Am188TMER, Am186TMER user manual Index

Master mode, 8-16

INT2 signal (Maskable Interrupt Request 2), 3-6INT3 Control Register

Master mode, 8-16

INT3 signal (Maskable Interrupt Request 3), 3-6INT4 Control Register

Master mode, 8-17

INT4 signal (Maskable Interrupt Request 4), 3-6INTA0 signal (Interrupt Acknowledge 0), 3-6INTA1 signal (Interrupt Acknowledge 1), 3-6Integer data type, 2-8

Internal memory debug modes, 6-2disable, 6-2

external RAM interaction, 6-1show read enable, 6-2

Interrupt acknowledge, 8-8

Interrupt conditions and sequence, 8-4Interrupt control unit, 8-1

Interrupt controller registers Master mode, 8-13Slave mode, 8-29

Interrupt controller reset conditions, 8-9Interrupt enable flag (IF), 8-2Interrupt mask bit, 8-2

Interrupt Mask Register Master mode, 8-25Slave mode, 8-35Interrupt priority, 8-2,8-5Interrupt Request Register Master mode, 8-22

Slave mode, 8-32Interrupt return (IRET), 8-4Interrupt Status Register

Master mode, 8-21Slave mode, 8-31Interrupt Vector Register Slave mode, 8-37Interrupt vector table, 8-1

Interrupt-Enable Flag bit, 2-3Interrupts

array BOUNDs exception, 8-7breakpoint, 8-7

cascade mode, 8-11divide error exception, 8-6EOI, 8-12

ESC opcode exception, 8-7fully nested mode, 8-10Instruction exceptions, 8-3INTO overflow detected, 8-7Maskable and nonmaskable, 8-2Master mode operation, 8-10nonmaskable (NMI), 8-6

polled, 8-12Slave mode, 8-29

Slave mode nesting, 8-29Special fully nested mode, 8-12trace, 8-6

types, 8-1,8-6types, table of, 8-3unused opcode, 8-7

IREQ bit (Interrupt Request) Poll Register, 8-27

Poll Status Register, 8-26IRET, 8-4

IRQ signal (Slave Interrupt Request), 3-6

K

Key features and benefits, 1-1

L

L2-L0 field (Interrupt Type), 8-36LB2-LB0 field (Lower Boundary), 5-4LCS signal (Low Memory Chip Select), 3-7LOOP bit (Loopback), 11-2

Low Memory Chip Select Register, 5-6LTM bit (Level-Triggered Mode)

INT0 Control Register, 8-14

INT1 Control Register, 8-14

INT2 Control Register, 8-16

INT3 Control Register, 8-16

INT4 Control Register, 8-17

M

M/IO bit (Memory/I/O Space), 4-4

M6-M0 field (MCS Block Size), 5-10M6-M0 field (Refresh Base), 7-1Maskable interrupts, 8-2

Master mode operation, 8-10MC bit (Maximum Count Bit)

Timer 0 Mode/Control Register, 9-3

Timer 1 Mode/Control Register, 9-3

Timer 2 Mode/Control Register, 9-5MCS2-MCS0 signals (Midrange Memory Chip Selects

2-0), 3-7

MCS3 signal (Midrange Memory Chip Select 3), 3-7Memory

addressing modes, 2-10interface, 1-7operands, 2-10organization, 2-3

Memory Partition Register, 7-1

Index I-5