AMD Am188TMER, Am186TMER user manual DMA Channels on Reset, DMA Controller 10-13

Each DMA register can be modified while the channel is operating. If the CHG bit is set to 0 when the control register is written, the ST bit of the control register will not be modified by the write. If multiple channel registers are modified, an internally LOCKed string transfer should be used to prevent a DMA transfer from occurring between updates to the channel registers.

10.4.5DMA Channels on Reset

On reset, the state of the DMA channels is as follows:

νThe ST bit for each channel is reset.

νAny transfer in progress is aborted.

νThe values of the transfer count registers, source address registers, and destination address registers are undefined.

DMA Controller 10-13