AMD Am188TMER, Am186TMER user manual Index

DEN (Data Enable), 3-4DRQ1-DRQ0 (DMA Requests), 3-4DT/R (Data Transmit or Receive), 3-4HLDA (Bus Hold Acknowledge), 3-4HOLD (Bus Hold Request), 3-5IMDIS (Internal Memory Disable), 3-13INT0 (Maskable Interrupt Request 0), 3-5INT1 (Maskable Interrupt Request 1), 3-5INT2 (Maskable Interrupt Request 2), 3-6INT3 (Maskable Interrupt Request 3), 3-6INT4 (Maskable Interrupt Request 4), 3-6INTA0 (Interrupt Acknowledge 0), 3-6INTA1 (Interrupt Acknowledge 1), 3-6IRQ (Slave Interrupt Request), 3-6LCS (Lower Memory Chip Select), 3-7

MCS2-MCS0 (Midrange Memory Chip Selects 2-0), 3-7

MCS3 (Midrange Memory Chip Select 3), 3-7NMI (Nonmaskable Interrupt), 3-7

ONCE0 (ONCE Mode Request 0), 3-7

ONCE1 (ONCE Mode Request 1), 3-15PCS30-PCS0 (Peripheral Chip Selects 3-0), 3-8PCS5 (Peripheral Chip Select 5), 3-8

PCS6 (Peripheral Chip Select 6), 3-8PIO31-PIO0 (Programmable I/O Pins 31-0), 3-9RD (Read Strobe), 3-12

RES (Reset), 3-12

RFSH (Automatic Refresh), 3-7

RFSH2/ADEN (Refresh 2/Address Enable), 3-12RXD (Receive Data), 3-12

S2-S0 (Bus Cycle Status 2-0), 3-13S6 (Bus Cycle Status 6), 3-13SCLK (Serial Clock), 3-14SDATA (Serial Data), 3-14

SDEN1-SDEN0 (Serial Data Enables 1-0), 3-14SELECT (Slave Select), 3-5

SRDY (Synchronous Ready), 3-14

SREN (Show Read Enable), 3-13TMRIN0 (Timer Input 0), 3-14TMRIN1 (Timer Input 1), 3-15TMROUT0 (Timer Output 0), 3-15TMROUT1 (Timer Output 1), 3-15TXD (Transmit Data), 3-15

UCS (Upper Memory Chip Select), 3-15UZI (Upper Zero Indicate), 3-15

WB (Write Byte), 3-16

WHB (Write High Byte), 3-16

WLB (Write Low Byte), 3-16WR (Write Strobe), 3-17X1 (Crystal Input), 3-17

X2 (Crystal Output), 3-17SINC bit (Source Increment), 10-4Slave mode

interrupts, 8-29nesting, 8-29

SM/IO bit (Source Address Space Select), 10-3Software interrupt, 8-2

Special fully nested mode, 8-12Specific End-of-Interrupt Register

Slave mode, 8-36

SPI bit (Serial Port Interrupt In-Service), 8-23SPI bit (Serial Port Interrupt Mask), 8-25SPI bit (Serial Port Interrupt Request), 8-22SR field (Receive Data), 12-6

SR field (Show Read)

Internal Memory Chip Select Register, 6-3SRDY signal (Synchronous Ready), 3-14SREN signal (Show Read Enable), 3-13

ST bit (Start/Stop DMA Channel), 10-4Stack pointer register, 2-1

Stack Segment (SS) Register, 2-8Status and control registers, 2-1STP bit (Stop Bits), 11-3

String data type, 2-9Support products, 1-8

SYN1-SYN0 field (Synchronization Type), 10-4Synchronous Serial Control Register, 12-4Synchronous Serial Receive Register, 12-6Synchronous Serial Status Register, 12-3Synchronous Serial Transmit 0 Register, 12-5Synchronous Serial Transmit 1 Register, 12-5System clocks, 3-25

T

T4-T0 field (Interrupt Type), 8-37

T8-T0 field (Refresh Count), 7-2TC bit (Terminal Count), 10-4

TC15-TC0 field (Timer Compare Value), 9-7TC15-TC0 field (Timer Count Register), 10-5TC15-TC0 field (Timer Count Value), 9-6TDATA field (Transmit Data), 11-5

TDRQ bit (Timer Enable/Disable Request), 10-4TEMT bit (Transmitter Empty), 11-4

TF bit (Trace Flag)

Processor Status Flags Register, 2-3Thermal characteristics, xiv Third-party

development, 1-8products, xiv

THRE bit (Transmit Holding Register Empty), 11-4Timer 0 Count Register, 9-6

Timer 0 Interrupt Control Register Slave mode, 8-30

Timer 0 Maxcount Compare A Register, 9-7Timer 0 Maxcount Compare B Register, 9-7Timer 0 Mode and Control Register, 9-3

Index I-9