AMD Am188TMER Interrupt Vector Register INTVEC, Offset 20h Slave Mode, Bits 2-0 Reserved -Read as

8.4.10Interrupt Vector Register (INTVEC, Offset 20h) (Slave Mode)

Vector generation in Slave mode is exactly like that of an 8259A or 82C59A slave. The interrupt controller generates an 8-bit interrupt type that the CPU shifts left two bits (multiplies by four) to generate an offset into the interrupt vector table.

Figure 8-26 Interrupt Vector Register (INTVEC, offset 20h)

15 7 0

0 0 0 0 0 0 0 0

T4–T0

0 0 0

The INTVEC Register is undefined on reset.

Bits 15–8: Reserved —Read as 0.

Bits 7–3: Interrupt Type (T4–T0)—Sets the five most significant bits of the interrupt types for the internal interrupt type. The interrupt controller itself provides the lower three bits of the interrupt type, as determined by the priority level of the interrupt request. See Table 8-5, “INT2 and INT3 Control Registers (I2CON, I3CON, offsets 3Ch and 3Eh),” on page 8-16.

Bits 2–0: Reserved —Read as 0.

Interrupt Control Unit 8-37