AMD Am188TMER, Am186TMER user manual Once Mode Request 0 input, Midrange Memory Chip Select

LCS/ONCE0

Lower Memory Chip Select (output, synchronous, internal pullup)

ONCE Mode Request 0 (input)

—This pin indicates to the system that a memory access is in

LCS

progress to the lower memory block. The size of the lower memory

block is programmable up to 512 Kbyte. LCS is held High during a bus

hold condition.

—During reset, this pin and

indicate to the

ONCE0

UCS

/ONCE1

microcontroller the mode in which it should operate.

and

ONCE0

are sampled on the rising edge of

If both pins are asserted

ONCE1

RES.

Low, the microcontroller enters ONCE mode; otherwise, it operates

normally.

In ONCE mode, all pins assume a high-impedance state and remain in

that state until a subsequent reset occurs. To guarantee that the

microcontroller does not inadvertently enter ONCE mode,

has

ONCE0

a weak internal pullup resistor that is active only during a reset.

Midrange Memory Chip Select 3

MCS3/RFSH

(output, synchronous, internal pullup)

Automatic Refresh (output, synchronous)

—This pin indicates to the system that a memory access is in

MCS3

progress to the fourth region of the midrange memory block. The base

address and size of the midrange memory block are programmable.

is held High during a bus hold condition. In addition, this pin has

MCS3

a weak internal pullup resistor that is active during reset.

—This pin provides a signal timed for auto refresh to PSRAM

RFSH

devices. It is only enabled to function as a refresh pulse when the

PSRAM mode bit is set in the LMCS Register. An active Low pulse is

generated for 1.5 clock cycles with an adequate deassertion period to

ensure that overall auto refresh cycle time is met.

Midrange Memory Chip Selects

MCS2–MCS 0

(output, synchronous, internal pullup)

These pins indicate to the system that a memory access is in progress

to the corresponding region of the midrange memory block. The base

address and size of the midrange memory block are programmable.

MCS2–MCS0 are held High during a bus hold condition. In addition,

they have weak internal pullup resistors that are active during a reset.

Unlike the

and

chip selects, the MCS outputs assert with the

UCS

LCS

multiplexed AD address bus.

NMI

Nonmaskable Interrupt (input, synchronous, edge-sensitive)

This pin indicates to the microcontroller that an interrupt request has

occurred. The NMI signal is the highest priority hardware interrupt and,

unlike the INT4–INT0 pins, cannot be masked. The microcontroller

always transfers program execution to the location specified by the

nonmaskable interrupt vector in the microcontroller interrupt vector

table when NMI is asserted.

Although NMI is the highest priority interrupt source, it does not

participate in the priority resolution process of the maskable interrupts.

There is no bit associated with NMI in the interrupt in-service or interrupt

request registers. This means that a new NMI request can interrupt an

System Overview 3-7