AMD Am188TMER, Am186TMER Serial Port Transmit Data Register SPTD, Offset 84h, Bits 15-8 Reserved

11.2.3Serial Port Transmit Data Register (SPTD, Offset 84h)

Software writes this register (Figure 11-4)with data to be transmitted on the serial port. The transmitter is double-buffered, and the transmit section copies data from the transmit data register to the transmit shift register (which is not accessible to software) before transmitting the data.

Figure 11-3 Serial Port Transmit Data Register (SPTD, offset 84h)

15 7 0

Reserved

TDATA

The value of SPTD at reset is undefined.

Bits 15–8: Reserved

Bit 7–0: Transmit Data (TDATA) —This field is written with data to be transmitted on the serial port. The THRE bit in the Serial Port Status register indicates whether there is valid data in the SPTD register. To avoid overwriting data in the SPTD register, the THRE bit should be read as a 1 before writing this register. Writing this register causes the THRE bit to be reset.

Asynchronous Serial Port 11-5