System Overview | AMD Am186TMER, Am188TMER guide

The refresh control unit must be programmed before accessing PSRAM in LCS space. The refresh counter in the Clock Prescaler (CDRAM) Register must be configured with the required refresh interval value. The ending address of LCS space and the ready and wait- state generation in the LMCS Register must also be programmed.

The refresh counter reload value in the CDRAM Register should not be set to less than 18 (12h) in order to provide time for processor cycles within refresh. In PSRAM mode, the refresh address counter must be set to 0000h to prevent another chip select from asserting. LCS is held High during a refresh cycle. The A19–A0 bus is not used during refresh cycles. The LMCS Register must be configured to external Ready ignored (R2=1) with one wait state (R1–R0=01b), and the PSRAM mode enable bit (PSE) must be set to 1. See section 5.5.2 on page 5-6.

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AMD Am186TMER, Am188TMER user manual System Overview

Contents

Am186äER and Am188äER Microcontrollers User’s Manual Advanced Micro Devices, Inc. All rights reserved Hotline and World Wide Web Support Customer ServiceIf YOU have QUESTIONS, WE’RE Here to Help YOU Documentation and LiteraturePage Table of Contents Chip Select Unit Timer Control Unit Viii Table of Contents Chapter DMA Controller List of Figures PCS MCS Figure A-1 List of Tables Processor Release Level PRL Register High-Order Byte Values Xii Table of Contents Purpose of this Manual Introduction and OverviewDesign Philosophy Intended Audience AMD Documentation E86 Microcontroller Family Features and Performance KEY Features and BenefitsFeatures and Performance Distinctive Characteristics Features and Performance Am186ER Microcontroller Block Diagram Am188ER Microcontroller Block Diagram Application Considerations Clock Generation Memory Interface Serial Communications Port THIRD-PARTY Development Support Products Programming Register SETProgramming Processor Status Flags Register Bits 15-12 -Reserved Bit 3 Reserved Memory Organization and Address GenerationBit 5 Reserved Bit 1 Reserved I/O Space Instruction SET Instruction Set Mnemonic Instruction Name JB/JNAE OUT Segment Register Selection Rules SegmentsData Types Segment Register Implicit Segment Selection Rule Supported Data Types Register and Immediate Operands Memory Addressing Mode ExamplesAddressing Modes Memory Operands Pin Terminology System OverviewPIN Descriptions A19-A0 Address Bus output, three-state, synchronous Address Latch Enable output, synchronous Aden Asynchronous Ready input, asynchronous, level-sensitive Bus High Enable, Am186ER Microcontroller OnlyAddress Enable, Am186ER Microcontroller Only Three-state, output, synchronous Clock Output B output, synchronous Data Enable output, three-state, synchronousClock Output a output, synchronous DMA Requests input, synchronous, level-sensitive Maskable Interrupt Request 1 input, asynchronous Bus Hold Request input, synchronous, level-sensitiveMaskable Interrupt Request 0 input, asynchronous Slave Select input, asynchronous Maskable Interrupt Request 3 input, asynchronous Maskable Interrupt Request 2 input, asynchronousInterrupt Acknowledge 0 output, synchronous Interrupt Acknowledge 1 output, synchronous Output, synchronous, internal pullup Once Mode Request 0 inputMidrange Memory Chip Select Automatic Refresh output, synchronous Latched Address Bit 1 output, synchronous Peripheral Chip Selects output, synchronousPeripheral Chip Select 5 output, synchronous Peripheral Chip Select 6 output, synchronous System Overview PIO No Associated Pin Power-On Reset Status PIO Pin Assignments-Numeric Listing Associated Pin PIO No Power-On Reset Status PIO Pin Assignments-Alphabetic Listing Read Strobe output, synchronous, three-state Reset input, asynchronous, level-sensitiveAddress Enable input, internal pullup Refresh 2 three-state, output, synchronous Bus Cycle Status output, three-state, synchronous Internal Memory Disable input, internal pullupShow Read Enable input, internal pullup Bus Cycle Status Bit 6 output, synchronous Serial Clock output, synchronous, three-state Serial Data Enables output, synchronousTimer Input 0 input, synchronous, edge-sensitive Serial Data input/output, synchronous Timer Output 1 output, synchronous Timer Input 1 input, synchronous, edge-sensitiveTimer Output 0 output, synchronous Once Mode Request 1 input, internal pullup Output, three-state, synchronous Power Supply inputWrite High Byte, Am186ER Microcontroller Only Write Low Byte, Am186ER Microcontroller Only Pins That Are Used by Emulators BUS Operation Clkouta A19-A0 Address AD7-AD0 Nonmultiplexed Address Bus Byte Write EnablesBUS Interface Unit Pseudo Static RAM Psram Support System Overview Maximum and Minimum Clock Frequencies Mode X1/X2 Clock and Power Management UnitPhase-Locked Loop PLL Min Crystal-Driven Clock Source External Source Clock Power-Save Operation System Clocks System Overview Peripheral Control Block OverviewPeripheral Control Block Peripheral Control Block Register Map Timer 1 Count Register Bit 15 Reserved Bit 13 Reserved Reset Configuration Register RESCON, Offset F6h Reset Configuration Register RESCON, offset F6h Processor Release Level Register PRL, Offset F4h Bits 7-0 Reserved -Value is undefined Power-Save Control Register PDCON, Offset F0h Bits 7-3 Reserved -Read back as Initialization and Processor Reset Divider Factor Registers not listed in this table are undefined at reset Peripheral Control Block Chip Select Unit Chip Select Unit Chip Select Timing Ready and WAIT-STATE ProgrammingChip Select Overlap Chip Select Registers Umcs Block Size Programming Values Upper Memory Chip Select Register UMCS, Offset A0hBit 15 Reserved-Set to Memory Block Starting Bits 11-8 Reserved Bits 6 Reserved- Set to Bits 5-3 Reserved- Set to Low Memory Chip Select Register LMCS, Offset A2h Lmcs Block Size Programming ValuesMemory Block Ending Bits 11-8 Reserved- Set to Midrange Memory Chip Select Register MMCS, Offset A6h Midrange Memory Chip Select Register MMCS, offset A6h Bits 8-3 Reserved -Set to MCS Block Size Programming PCS and MCS Auxiliary Register MPCS, Offset A8hBit 15 Reserved- Set to Total Block Individual Bits 5-3 Reserved -Set to Peripheral Chip Select Register PACS, Offset A4h Peripheral Chip Select Register PACS, offset A4h Low High Bits 6-4 Reserved -Set toPCS Address Ranges Line PCS3-PCS0 Wait-State Encoding Wait States Chip Select Unit Internal Memory Interaction with External RAMInternal Memory Internal Memory Disable Show Read EnableEmulator and Debug Modes Internal Memory Chip Select Register IMCS, Offset ACh Bits 8-0 Reserved -Set to Internal Memory Bits 8-0 Reserved -Read back as Refresh Control UnitMemory Partition Register MDRAM, Offset E0h Refresh Control Unit Enable RCU Register EDRAM, Offset E4h Clock Prescaler Register CDRAM, Offset E2hBits 14-9 Reserved -Read back as Interrupt Type Interrupt Control UnitDefinitions of Interrupt Terms Interrupt Vector Table Interrupt Mask Bit Interrupt Enable Flag ifMaskable and Nonmaskable Interrupts Interrupt Priority Software Exceptions Am186ER and Am188ER Microcontroller Interrupt TypesOverall Interrupt Conditions and Sequence Interrupt Priority Nonmaskable Interrupts and Software Interrupt PriorityMaskable Hardware Interrupt Priority Trace Interrupt Interrupt Type 01h Divide Error Exception Interrupt Type 00hSoftware Exceptions, Traps, and NMI Nonmaskable Interrupt-NMI Interrupt Type 02h Array Bounds Exception Interrupt Type 05h Breakpoint Interrupt Interrupt Type 03hInto Detected Overflow Exception Interrupt Type 04h Unused Opcode Exception Interrupt Type 06h Interrupt Acknowledge External Interrupt Acknowledge Bus Cycles Interrupt Controller Reset Conditions Master Mode Operation Fully Nested Mode Cascade Mode Cascade Mode Interrupt Controller Connections Special Fully Nested Mode Operation in a Polled EnvironmentEnd-of-Interrupt Write to the EOI Register Master Mode Interrupt Controller Registers Value of I0CON and I1CON at reset is 000Fh Priority Level Bits 15-5 Reserved -Set to 3 INT4 Control Register I4CON, Offset 40h Master Mode INT4 Control Register I4CON, offset 40h Bits 15-4 Reserved -Set to Value of Wdcon at reset is 000Fh Bits 15-5 Reserved -Set to Bit 4 Reserved-Set to Serial Port Interrupt Control Register SPICON, offset 44h Interrupt Status Register INTSTS, Offset 30h Master Mode 10 Interrupt Status Register INTSTS, offset 30h Interrupt Request Register REQST, Offset 2Eh Master Mode Bits 15-11 Reserved In-Service Register INSERV, Offset 2Ch Master Mode 12 In-Service Register INSERV, offset 2Ch Priority Mask Register PRIMSK, Offset 2Ah Master Mode Priority Field Mask Master Mode PR2-PR0 Interrupt Mask Register IMASK, Offset 28h Master Mode 14 Interrupt Mask Register IMASK, offset 28h Poll Status Register POLLST, Offset 26h Master Mode Bits 14-5 Reserved -Set to Poll Register POLL, Offset 24h Master Mode 16 Poll Register POLL, offset 24h End-of-Interrupt Register EOI, Offset 22h Master Mode Bits 14-5 Reserved Slave Mode Operation Slave Mode Interrupt NestingSlave Mode Interrupt Controller Registers These registers are set to 000Fh on reset Interrupt Status Register INTSTS, Offset 30h Slave Mode 20 Interrupt Status Register INTSTS, offset 30h Interrupt Request Register REQST, Offset 2Eh Slave Mode 21 Interrupt Request Register REQST, offset 2Eh In-Service Register INSERV, Offset 2Ch Slave Mode 22 In-Service Register INSERV, offset 2Ch Priority Mask Register PRIMSK, Offset 2Ah Slave Mode Priority Field Mask Slave Mode PR2-PR0 Interrupt Mask Register IMASK, Offset 28h Slave Mode 24 Interrupt Mask Register IMASK, offset 28h Bits 15-3 Reserved -Write as 25 Specific End-of-Interrupt Register EOI, offset 22h Interrupt Vector Register INTVEC, Offset 20h Slave Mode Bits 15-8 Reserved -Read asBits 2-0 Reserved -Read as Interrupt Control Unit Timer Control Unit Timer Control UnitTimer Control Unit Register Summary Offsetfrom Programmable Registers Timer Operating Frequency Bits 11-6 Reserved -Set to Timer Control Unit Timer 2 Mode and Control Register T2CON, Offset 66h Bits 12-6 Reserved -Set toBits 4-1 Reserved -Set to TC15-TC0 Value of these registers at reset is undefined Timer Control Unit DMA Controller Register Summary Offsetfrom DMA ControllerDMA Operation DMA Controller 10-1 Programmable DMA Registers 10-2 DMA Controller DMA Control Registers D0CON, Offset CAh, D1CON, Offset DAh DMA Controller 10-3 Synchronization Type Sync Type10-4 DMA Controller DMA Transfer Count Registers D0TC, D1TC, offsets C8h and D8h DMA Controller 10-5 10-6 DMA Controller DMA Controller 10-7 10-8 DMA Controller DMA Controller 10-9 DMA Requests 10-10 DMA Controller Destination Synchronization Timing Synchronization TimingSource Synchronization Timing DMA Controller 10-11 DMA Programming DMA AcknowledgeDMA Priority 10-12 DMA Controller DMA Channels on Reset DMA Controller 10-13 10-14 DMA Controller Asynchronous Serial Port Asynchronous Serial Port Register Summary OffsetfromAsynchronous Serial Port 11-1 Serial Port Control Register SPCT, Offset 80h 11-2 Asynchronous Serial Port Parity Mode Bit Settings Asynchronous Serial Port 11-3 Serial Port Status Register SPSTS, Offset 82h Bits 15-7 Reserved -Set to11-4 Asynchronous Serial Port Serial Port Transmit Data Register SPTD, Offset 84h Bits 15-8 ReservedAsynchronous Serial Port 11-5 Serial Port Receive Data Register SPRD, Offset 86h 11-6 Asynchronous Serial Port Serial Port Baud Rate Divisor Register SPBAUD, Offset 88h Asynchronous Serial Port 11-7 11-8 Asynchronous Serial Port Synchronous Serial Interface Synchronous Serial Interface Register Summary Offset fromSynchronous Serial Interface 12-1 Four-Pin Interface 12-2 Synchronous Serial Interface Synchronous Serial Status Register SSS, Offset 10h Synchronous Serial Interface 12-3 Synchronous Serial Control Register SSC, Offset 12h Bits 15-6 Reserved -Set toBits 3-2 Reserved -Set to Bits 15-8 Reserved -Set to Synchronous Serial Interface 12-5 Synchronous Serial Receive Register SSR, Offset 18h 12-6 Synchronous Serial Interface SSI Programming Synchronous Serial Interface 12-7 Synchronous Serial Interface Multiple Write Synchronous Serial Interface Multiple Read Programmable I/O Pins Programmable I/O Pins 13-1 Registers PIOMODE1, 76h PDIR0, 78h PDATA0, 7Ah 13-2 PIO Mode 0 Register PIOMODE0, Offset 70h PIO Mode RegistersPIO Mode 1 Register PIOMODE1, Offset 76h PIO Mode and PIO Direction Settings Pin Function PIO Direction 0 Register PDIR0, Offset 72h PIO Direction RegistersPIO Direction 1 Register PDIR1, Offset 78h 13-4 PIO Data Register 1 PDATA1, Offset 7Ah Programmable I/O Pins 13-5PIO Data Registers PIO Data Register 0 PDATA0, Offset 74h 13-6 Register Summary Register Summary Rescon T1CMPB Figure A-1 Internal Register Summary Memory Partition Register Mdram DMA 0 Control Register D0CON Internal Memory Chip Select Register Imcs Serial Port Baud Rate Divisor Register Spbaud PMODE15-PMODE0 Timer 2 Maxcount Compare a Register T2CMPA Timer 0 Maxcount Compare B Register T0CMPB Sfnm Interrupt Request Register Reqst Master Mode Interrupt Request Register Reqst Slave Mode Interrupt Mask Register Imask Interrupt Vector Register Intvec Slave Mode Index Index Index Index Index Index Index Index Index Index Index