AMD Am186TMER, Am188TMER user manual Index

DHLT (DMA Halt), 8-21,8-31	RDATA (Receive Data), 11-6
DINC (Destination Increment), 10-3	RDR (Receive Data Ready), 11-4
DM/IO (Destination Address Space Select), 10-3	RE (Internal Ram Enable), 6-3
DR/DT (Data Receive/Transmit Complete), 12-3	RE/TE (Receive/Transmit Error Detect), 12-3
DSA15-DSA0 (DMA Source Address Low), 10-9	RIU (Register in Use), 9-3
DSA19-DSA16 (DMA Source Address High), 10-8	RMODE (Receive Mode), 11-3
E (Enable RCU), 7-2	RSIE (Receive Status Interrupt Enable), 11-3
EN (Enable Bit), 9-3,9-5	RTG (Retrigger Bit), 9-3
EX (Pin Selector), 5-11	RXIE (Receive Data Ready Interrupt Enable), 11-2
EXT (External Clock Bit), 9-4	S/M (Slave/Master), 4-4
FER (Framing Error), 11-4	S4-S0 (Poll Status), 8-26–8-27
I4-I0 (Interrupt In-Service), 8-23	S4-S0 (Source Interrupt Type), 8-28
I4-I0 (Interrupt Mask), 8-25	SD (Send Data), 12-5
I4-I0 (Interrupt Requests), 8-22	SDEC (Source Decrement), 10-4
IF (Interrupt-Enable Flag), 2-3	SF (Sign Flag), 2-3
INH (Inhibit Bit), 9-3,9-5	SFNM (Special Fully Nested Mode), 8-14
INT (Interrupt Bit), 9-3,9-5	SINC (Source Increment), 10-4
INT (Interrupt), 10-4	SM/IO (Source Address Space Select), 10-3
IREQ (Interrupt Request), 8-26–8-27	SPI (Serial Port Interrupt In-Service), 8-23
L2-L0 (Interrupt Type), 8-36	SPI (Serial Port Interrupt Mask), 8-25
LB2-LB0 (Lower Boundary), 5-4	SPI (Serial Port Interrupt Request), 8-22
LOOP (Loopback), 11-2	SR (Receive Data), 12-6
LTM (Level-Triggered Mode), 8-14,8-16–8-17	SR (Show Read), 6-3
M/IO (Memory/I/O Space), 4-4	ST (Start/Stop DMA Channel), 10-4
M6-M0 (MCS Block Size), 5-10	STP (Stop Bits), 11-3
M6-M0 (Refresh Base), 7-1	SYN1-SYN0 (Synchronization Type), 10-4
MC (Maximum Count Bit), 9-3,9-5	T4-T0 (Interrupt Type), 8-37
MS (Memory/I/O Space Selector), 5-11	T8-T0 (Refresh Count), 7-2
MSK (Interrupt Mask), 8-18	TC (Terminal Count), 10-4
MSK (Mask), 8-14,8-16–8-17,8-19–8-20,8-30	TC15-TC0 (Timer Compare Value), 9-7
NSPEC (Non-Specific EOI), 8-28	TC15-TC0 (Timer Count Register), 10-5
OER (Overrun Error), 11-4	TC15-TC0 (Timer Count Value), 9-6
OF (Overflow Flag), 2-2	TDATA (Transmit Data), 11-5
P (Prescaler Bit), 9-3	TDRQ (Timer Enable/Disable Request), 10-4
P (Relative Priority), 10-4	TEMT (Transmitter Empty), 11-4
PB (SSI Port Busy), 12-3	TF (Trace Flag), 2-3
PDATA15-PDATA0 (PIO Data BIts), 13-5	THRE (Transmit Holding Register Empty), 11-4
PDATA31-PDATA16 (PIO Data BIts), 13-5	TMODE (Transmit Mode), 11-3
PDIR15-PDIR0 (PIO Direction Bits), 13-4	TMR (Timer Interrupt In-Service), 8-23
PDIR31-PDIR16 (PIO Direction Bits), 13-4	TMR (Timer Interrupt Mask), 8-25
PER (Parity Error), 11-4	TMR (Timer Interrupt Request), 8-22
PF (Parity Flag), 2-3	TMR0 (Timer 0 Interrupt In-Service), 8-33
PMODE (Parity Mode), 11-3	TMR0 (Timer 0 Interrupt Mask), 8-35
PMODE15-PMODE0 (PIO Mode Bits), 13-3	TMR0 (Timer 0 Interrupt Request), 8-32
PMODE31-PMODE16 (PIO Mode Bits), 13-3	TMR2-TMR0 (Timer Interrupt Request), 8-21,8-31
PR2-PR0 (Priority Level), 8-30	TMR2-TMR1 (Timer 2/Timer 1 Interrupt In-Service),
PR2-PR0 (Priority), 8-15–8-20	8-33
PRL (Processor Release Level), 4-6	TMR2-TMR1 (Timer 2/Timer 1 Interrupt Mask), 8-35
PRM2-PRM0 (Priority Field Mask), 8-24,8-34	TRM2-TMR1 (Timer2/Timer1 Interrupt Request), 8-
PSE (PSRAM Mode Enable), 5-7	32
PSEN (Enable Power-Save Mode), 4-7	TXIE (Transmit Holding Register Empty Interrupt
R19-R8 (Relocation Address Bits), 4-4	Enable), 11-2
R1-R0 (Wait State Value), 5-5,5-7,5-9,5-11,5-13	WD (Virtual Watchdog Timer Interrupt Request), 8-
R2 (Ready Mode), 5-5,5-7,5-9,5-11,5-13	22
R3 (Wait State Value), 5-13	WD (Watchdog Timer Interrupt In-Service), 8-23
RC (Reset Configuration), 4-5	WD (Watchdog Timer Interrupt Mask), 8-25
RC8-RC0 (Refresh Counter Reload Value), 7-2	WLGN (Word Length), 11-3

I-2 Index