AMD Am188TMER, Am186TMER user manual Timer Control Unit

8.2 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.2.1 Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.2.2 Cascade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.2.3 Special Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.2.4 Operation in a Polled Environment . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.2.5 End-of-Interrupt Write to the EOI Register . . . . . . . . . . . . . . . . . 8-12

8.3 Master Mode Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . 8-13

8.3.1INT0 and INT1 Control Registers

(I0CON, Offset 38h, I1CON, Offset 3Ah). . . . . . . . . . . . . . . . . . . 8-14

8.3.2INT2 and INT3 Control Registers

(I2CON, Offset 3Ch, I3CON, Offset 3Eh) . . . . . . . . . . . . . . . . . . 8-16 8.3.3 INT4 Control Register (I4CON, Offset 40h). . . . . . . . . . . . . . . . . 8-17

8.3.4Timer and DMA Interrupt Control Registers

(TCUCON, Offset 32h, DMA0CON, Offset 34h, DMA1CON,

Offset 36h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

8.3.5Watchdog Timer Interrupt Control Register

(WDCON, Offset 42h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 8.3.6 Serial Port Interrupt Control Register (SPICON, Offset 44h). . . . 8-20 8.3.7 Interrupt Status Register (INTSTS, Offset 30h). . . . . . . . . . . . . . 8-21 8.3.8 Interrupt Request Register (REQST, Offset 2Eh) . . . . . . . . . . . . 8-22 8.3.9 In-Service Register (INSERV, Offset 2Ch) . . . . . . . . . . . . . . . . . 8-23 8.3.10 Priority Mask Register (PRIMSK, Offset 2Ah) . . . . . . . . . . . . . . . 8-24 8.3.11 Interrupt Mask Register (IMASK, Offset 28h) . . . . . . . . . . . . . . . 8-25 8.3.12 Poll Status Register (POLLST, Offset 26h) . . . . . . . . . . . . . . . . . 8-26 8.3.13 Poll Register (POLL, Offset 24h) . . . . . . . . . . . . . . . . . . . . . . . . . 8-27 8.3.14 End-of-Interrupt Register (EOI, Offset 22h). . . . . . . . . . . . . . . . . 8-28

8.4 Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 8.4.1 Slave Mode Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 8.4.2 Slave Mode Interrupt Controller Registers . . . . . . . . . . . . . . . . . 8-29

8.4.3Timer and DMA Interrupt Control Registers

(T0INTCON, Offset 32h, T1INTCON, Offset 38h, T2INTCON,

Offset 3Ah, DMA0CON, Offset 34h, DMA1CON, Offset 36h) . . . 8-30 8.4.4 Interrupt Status Register (INTSTS, Offset 30h). . . . . . . . . . . . . . 8-31 8.4.5 Interrupt Request Register (REQST, Offset 2Eh) . . . . . . . . . . . . 8-32 8.4.6 In-Service Register (INSERV, Offset 2Ch) . . . . . . . . . . . . . . . . . 8-33 8.4.7 Priority Mask Register (PRIMSK, Offset 2Ah) . . . . . . . . . . . . . . . 8-34 8.4.8 Interrupt Mask Register (IMASK, Offset 28h) . . . . . . . . . . . . . . . 8-35 8.4.9 Specific End-of-Interrupt Register (EOI, Offset 22h) . . . . . . . . . . 8-36 8.4.10 Interrupt Vector Register (INTVEC, Offset 20h) . . . . . . . . . . . . . 8-37

CHAPTER 9 TIMER CONTROL UNIT

9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.2 Programmable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.2.1 Timer Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.2.2Timer 0 and Timer 1 Mode and Control Registers (T0CON,

Offset 56h, T1CON, Offset 5Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2.3 Timer 2 Mode and Control Register (T2CON, Offset 66h) . . . . . . 9-5

9.2.4Timer Count Registers (T0CNT, Offset 50h, T1CNT,

Offset 58h, T2CNT, Offset 60h). . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.2.5Timer Maxcount Compare Registers (T0CMPA, Offset 52h,

T0CMPB, Offset 54h, T1CMPA, Offset 5Ah, T1CMPB,

Offset 5Ch, T2CMPA, Offset 62h) . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

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