AMD Am188TMER DMA Transfer Count Registers D0TC, D1TC, offsets C8h and D8h, DMA Controller 10-5

10.3.2DMA Transfer Count Registers (D0TC, Offset C8h, D1TC, Offset D8h)

Each DMA channel maintains a 16-bit DMA Transfer Count register (DTC). This register is decremented after every DMA cycle, regardless of the state of the TC bit in the DMA Control register. However, if the TC bit in the DMA control word is set or if unsynchronized transfers are programmed, DMA activity terminates when the Transfer Count register reaches 0.

Figure 10-3 DMA Transfer Count Registers (D0TC, D1TC, offsets C8h and D8h)

15 7 0

TC15–TC0

The value of D0TC and D1TC at reset is undefined.

Bits 15–0: DMA Transfer Count (TC15–TC0) —Contains the transfer count for a DMA channel. Value is decremented by 1 after each transfer.

DMA Controller 10-5