AMD Am186TMER, Am188TMER user manual Index

Power-Save Control (PDCON, Offset F0h), 4-7Priority Mask (PRIMSK, Offset 2Ah), 8-24,8-34Processor Release Level (PRL, Offset F4), 4-6Reset Configuration (RESCON, Offset F6h), 4-5Serial Port Baud Rate Divisor (SPBAUD, Offset

88h), 11-7

Serial Port Control (SPCT, Offset 80h), 11-2Serial Port Interrupt Control (SPICON, Offset 44h)

Master mode, 8-20

Serial Port Receive Data (SPRD, Offset 86h), 11-6Serial Port Status (SPSTS, Offset 82h), 11-4Serial Port Transmit (SPTD, Offset 84h), 11-5Specific End-of-Interrupt (EOI, OFfset 22h), 8-36Synchronous Serial Control (SSC, Offset 12h), 12-4Synchronous Serial Receive (SSR, Offset 18h), 12-6Synchronous Serial Status (SSS, Offset 10h), 12-3Synchronous Serial Transmit 0 (SSD0, Offset 14h),

12-5

Synchronous Serial Transmit 1 (SSD1, Offset 14h), 12-5

Timer 0 Count (T0CNT, Offset 50h), 9-6

Timer 0 Interrupt Control (T0INTCON, Offset 32h), 8-30

Timer 0 Maxcount Compare A (T0CMPA, Offset 52h), 9-7

Timer 0 Maxcount Compare B (T0CMPB, Offset 54h), 9-7

Timer 0 Mode and Control (T0CON, Offset 56h), 9-3Timer 1 Count (T1CNT, Offset 58h), 9-6

Timer 1 Interrupt Control (T1INTCON, Offset 38h), 8-30

Timer 1 Maxcount Compare A (T1CMPA, Offset 5Ah), 9-7

Timer 1 Maxcount Compare B (T1CMPB, Offset 5Ch), 9-7

Timer 1 Mode and Control (T1CON, Offset 5Eh), 9-3Timer 2 Count (T2CNT, Offset 60h), 9-6

Timer 2 Interrupt Control (T2INTCON, Offset 3Ah), 8-30

Timer 2 Maxcount Compare A (T2CMPA, Offset 62h), 9-7

Timer 2 Mode and Control (T2CON, Offset 66h), 9-5Timer Interrupt Control (TCUCON, Offset 32h), 8-18Upper Memory Chip Select (UMCS, Offset A0h), 5-4Watchdog Timer Interrupt Control (WDCON, Offset

42h), 8-19RES signal (Reset)

definition, 3-12

interrupt controller conditions, 8-9Reset Configuration Register, 4-5Return from interrupt, 8-4

RFSH signal (Automatic Refresh), 3-7RFSH2 signal (Refresh 2), 3-12

RIU bit (Register in Use)

Timer 0 Mode/Control Register, 9-3

Timer 1 Mode/Control Register, 9-3

RMODE bit (Receive Mode), 11-3

RSIE bit (Receive Status Interrupt Enable), 11-3RTG bit (Retrigger Bit)

Timer 0 Mode/Control Register, 9-3

Timer 1 Mode/Control Register, 9-3RXD signal (Receive Data), 3-12

RXIE bit (Receive Data Ready Interrupt Enable), 11-2

S

S/M bit (Slave/Master), 4-4

S2-S0 signals (Bus Cycle Status 2-0), 3-13S4-S0 field (Poll Status)

Poll Register, 8-27

Poll Status Register, 8-26

S4-S0 field (Source Vector Type), 8-28S6 signal (Bus Cycle Status 6), 3-13SCLK signal (Serial Clock), 3-14

SD field (Send Data), 12-5SDATA signal (Serial Data), 3-14SDEC bit (Source Decrement), 10-4

SDEN1-SDEN0 signals (Serial Data Enables 1-0), 3-14Segment registers, 2-1,2-8

SELECT signal (Slave Select), 3-5Serial port, 1-7

Serial Port Baud Rate Divisor Register, 11-7Serial Port Control Register, 11-2

Serial Port Interrupt Control Register Master mode, 8-20

Serial Port Receive Data Register, 11-6Serial Port Status Register, 11-4Serial Port Transmit Data Register, 11-5SF bit (Sign Flag)

Processor Status Flags Register, 2-3SFNM bit (Special Fully Nested Mode), 8-14Show read enable, 6-2

Sign Flag bit, 2-3Signal description

A1 (Latched Address Bit 1), 3-8

A19-A0 (Address Bus), 3-1

A2 (Latched Address Bit 2), 3-9AD15-AD8 (Address and Data Bus), 3-2AD7-AD0 (Address and Data Bus), 3-1ADEN (Address Enable), 3-3,3-12ALE (Address Latch Enable), 3-2AO15-AO7 (Address-Only Bus), 3-2ARDY (Asynchronous Ready), 3-3BHE (Bus High Enable), 3-3CLKOUTA (Clock Output A), 3-4CLKOUTB (Clock Output B), 3-4CLKSEL1 (Clock Select 1), 3-13CLKSEL2 (Clock Select 2), 3-15

I-8 Index