Emulator and Debug Modes, Internal Memory Disable | AMD Am186TMER

6.3EMULATOR AND DEBUG MODES

There are two debug modes associated with the internal memory. One mode allows users to disable the internal RAM, and the other mode makes it possible to drive data on the external data bus during internal RAM read cycles.

Normal operation of internal RAM has all control signals for reads and writes and data for writes visible externally. Accesses to internal memory can be detected externally by comparing the address on A19–A0 with the address space of the internal memory.

6.3.1Internal Memory Disable

When this mode is activated, the internal RAM is disabled and all accesses into the internal memory space are made externally for debugging purposes. This mode is activated by pulling the S1/IMDIS pin Low during reset. To use this debug mode, internal memory space must first be activated via the IMCS Register as described on page 6-3.

6.3.2Show Read Enable

When this mode is activated, the data from the internal RAM read cycles are driven on the AD15–AD0 bus. Note that if a byte read is being shown, the unused byte will also be driven on the AD15–AD0 bus. This mode can be activated externally by pulling the S0/SREN pin Low during reset or by setting the SR bit in the IMCS Register. If this feature is activated externally using the SREN pin, the value of the SR bit is ignored. Many emulators assert the SREN pin. For more details, see the IMCS Register information on page 6-3.

During an internal memory read with show read enabled, the address will be driven on the

AD bus during t1 and t2. The data being read will be driven on the AD bus during t3 and t4 by the Am186ER or Am188ER microcontrollers. Special system care must be taken to

avoid bus contention, since normal reads have the AD bus three-stated during t2, t3, and t4. It is best to ensure that no external device overlaps the internal memory space.

6-2	Internal Memory

Image 84

AMD Am186TMER, Am188TMER user manual Emulator and Debug Modes, Internal Memory Disable, Show Read Enable

Contents

Am186äER and Am188äER Microcontrollers User’s Manual Advanced Micro Devices, Inc. All rights reserved Customer Service If YOU have QUESTIONS, WE’RE Here to Help YOUHotline and World Wide Web Support Documentation and LiteraturePage Table of Contents Chip Select Unit Timer Control Unit Viii Table of Contents Chapter DMA Controller List of Figures PCS MCS Figure A-1 List of Tables Processor Release Level PRL Register High-Order Byte Values Xii Table of Contents Introduction and Overview Design PhilosophyPurpose of this Manual Intended Audience AMD Documentation E86 Microcontroller Family Features and Performance KEY Features and BenefitsFeatures and Performance Distinctive Characteristics Features and Performance Am186ER Microcontroller Block Diagram Am188ER Microcontroller Block Diagram Application Considerations Clock Generation Memory Interface Serial Communications Port THIRD-PARTY Development Support Products Programming Register SETProgramming Processor Status Flags Register Bits 15-12 -Reserved Memory Organization and Address Generation Bit 5 ReservedBit 3 Reserved Bit 1 Reserved I/O Space Instruction SET Instruction Set Mnemonic Instruction Name JB/JNAE OUT Segments Data TypesSegment Register Selection Rules Segment Register Implicit Segment Selection Rule Supported Data Types Memory Addressing Mode Examples Addressing ModesRegister and Immediate Operands Memory Operands System Overview PIN DescriptionsPin Terminology A19-A0 Address Bus output, three-state, synchronous Address Latch Enable output, synchronous Aden Bus High Enable, Am186ER Microcontroller Only Address Enable, Am186ER Microcontroller OnlyAsynchronous Ready input, asynchronous, level-sensitive Three-state, output, synchronous Data Enable output, three-state, synchronous Clock Output a output, synchronousClock Output B output, synchronous DMA Requests input, synchronous, level-sensitive Bus Hold Request input, synchronous, level-sensitive Maskable Interrupt Request 0 input, asynchronousMaskable Interrupt Request 1 input, asynchronous Slave Select input, asynchronous Maskable Interrupt Request 2 input, asynchronous Interrupt Acknowledge 0 output, synchronousMaskable Interrupt Request 3 input, asynchronous Interrupt Acknowledge 1 output, synchronous Once Mode Request 0 input Midrange Memory Chip SelectOutput, synchronous, internal pullup Automatic Refresh output, synchronous Peripheral Chip Selects output, synchronous Peripheral Chip Select 5 output, synchronousLatched Address Bit 1 output, synchronous Peripheral Chip Select 6 output, synchronous System Overview PIO No Associated Pin Power-On Reset Status PIO Pin Assignments-Numeric Listing Associated Pin PIO No Power-On Reset Status PIO Pin Assignments-Alphabetic Listing Reset input, asynchronous, level-sensitive Address Enable input, internal pullupRead Strobe output, synchronous, three-state Refresh 2 three-state, output, synchronous Internal Memory Disable input, internal pullup Show Read Enable input, internal pullupBus Cycle Status output, three-state, synchronous Bus Cycle Status Bit 6 output, synchronous Serial Data Enables output, synchronous Timer Input 0 input, synchronous, edge-sensitiveSerial Clock output, synchronous, three-state Serial Data input/output, synchronous Timer Input 1 input, synchronous, edge-sensitive Timer Output 0 output, synchronousTimer Output 1 output, synchronous Once Mode Request 1 input, internal pullup Power Supply input Write High Byte, Am186ER Microcontroller OnlyOutput, three-state, synchronous Write Low Byte, Am186ER Microcontroller Only Pins That Are Used by Emulators BUS Operation Clkouta A19-A0 Address AD7-AD0 Byte Write Enables BUS Interface UnitNonmultiplexed Address Bus Pseudo Static RAM Psram Support System Overview Clock and Power Management Unit Phase-Locked Loop PLLMaximum and Minimum Clock Frequencies Mode X1/X2 Min Crystal-Driven Clock Source External Source Clock Power-Save Operation System Clocks System Overview Peripheral Control Block OverviewPeripheral Control Block Peripheral Control Block Register Map Timer 1 Count Register Bit 15 Reserved Bit 13 Reserved Reset Configuration Register RESCON, Offset F6h Reset Configuration Register RESCON, offset F6h Processor Release Level Register PRL, Offset F4h Bits 7-0 Reserved -Value is undefined Power-Save Control Register PDCON, Offset F0h Bits 7-3 Reserved -Read back as Initialization and Processor Reset Divider Factor Registers not listed in this table are undefined at reset Peripheral Control Block Chip Select Unit Chip Select Unit Chip Select Timing Ready and WAIT-STATE ProgrammingChip Select Overlap Chip Select Registers Upper Memory Chip Select Register UMCS, Offset A0h Bit 15 Reserved-Set toUmcs Block Size Programming Values Memory Block Starting Bits 11-8 Reserved Bits 6 Reserved- Set to Bits 5-3 Reserved- Set to Low Memory Chip Select Register LMCS, Offset A2h Lmcs Block Size Programming ValuesMemory Block Ending Bits 11-8 Reserved- Set to Midrange Memory Chip Select Register MMCS, Offset A6h Midrange Memory Chip Select Register MMCS, offset A6h Bits 8-3 Reserved -Set to PCS and MCS Auxiliary Register MPCS, Offset A8h Bit 15 Reserved- Set toMCS Block Size Programming Total Block Individual Bits 5-3 Reserved -Set to Peripheral Chip Select Register PACS, Offset A4h Peripheral Chip Select Register PACS, offset A4h Bits 6-4 Reserved -Set to PCS Address Ranges LineLow High PCS3-PCS0 Wait-State Encoding Wait States Chip Select Unit Internal Memory Interaction with External RAMInternal Memory Internal Memory Disable Show Read EnableEmulator and Debug Modes Internal Memory Chip Select Register IMCS, Offset ACh Bits 8-0 Reserved -Set to Internal Memory Refresh Control Unit Memory Partition Register MDRAM, Offset E0hBits 8-0 Reserved -Read back as Refresh Control Unit Enable RCU Register EDRAM, Offset E4h Clock Prescaler Register CDRAM, Offset E2hBits 14-9 Reserved -Read back as Interrupt Control Unit Definitions of Interrupt TermsInterrupt Type Interrupt Vector Table Interrupt Enable Flag if Maskable and Nonmaskable InterruptsInterrupt Mask Bit Interrupt Priority Software Exceptions Am186ER and Am188ER Microcontroller Interrupt TypesOverall Interrupt Conditions and Sequence Interrupt Priority Nonmaskable Interrupts and Software Interrupt PriorityMaskable Hardware Interrupt Priority Divide Error Exception Interrupt Type 00h Software Exceptions, Traps, and NMITrace Interrupt Interrupt Type 01h Nonmaskable Interrupt-NMI Interrupt Type 02h Breakpoint Interrupt Interrupt Type 03h Into Detected Overflow Exception Interrupt Type 04hArray Bounds Exception Interrupt Type 05h Unused Opcode Exception Interrupt Type 06h Interrupt Acknowledge External Interrupt Acknowledge Bus Cycles Interrupt Controller Reset Conditions Master Mode Operation Fully Nested Mode Cascade Mode Cascade Mode Interrupt Controller Connections Special Fully Nested Mode Operation in a Polled EnvironmentEnd-of-Interrupt Write to the EOI Register Master Mode Interrupt Controller Registers Value of I0CON and I1CON at reset is 000Fh Priority Level Bits 15-5 Reserved -Set to 3 INT4 Control Register I4CON, Offset 40h Master Mode INT4 Control Register I4CON, offset 40h Bits 15-4 Reserved -Set to Value of Wdcon at reset is 000Fh Bits 15-5 Reserved -Set to Bit 4 Reserved-Set to Serial Port Interrupt Control Register SPICON, offset 44h Interrupt Status Register INTSTS, Offset 30h Master Mode 10 Interrupt Status Register INTSTS, offset 30h Interrupt Request Register REQST, Offset 2Eh Master Mode Bits 15-11 Reserved In-Service Register INSERV, Offset 2Ch Master Mode 12 In-Service Register INSERV, offset 2Ch Priority Mask Register PRIMSK, Offset 2Ah Master Mode Priority Field Mask Master Mode PR2-PR0 Interrupt Mask Register IMASK, Offset 28h Master Mode 14 Interrupt Mask Register IMASK, offset 28h Poll Status Register POLLST, Offset 26h Master Mode Bits 14-5 Reserved -Set to Poll Register POLL, Offset 24h Master Mode 16 Poll Register POLL, offset 24h End-of-Interrupt Register EOI, Offset 22h Master Mode Bits 14-5 Reserved Slave Mode Operation Slave Mode Interrupt NestingSlave Mode Interrupt Controller Registers These registers are set to 000Fh on reset Interrupt Status Register INTSTS, Offset 30h Slave Mode 20 Interrupt Status Register INTSTS, offset 30h Interrupt Request Register REQST, Offset 2Eh Slave Mode 21 Interrupt Request Register REQST, offset 2Eh In-Service Register INSERV, Offset 2Ch Slave Mode 22 In-Service Register INSERV, offset 2Ch Priority Mask Register PRIMSK, Offset 2Ah Slave Mode Priority Field Mask Slave Mode PR2-PR0 Interrupt Mask Register IMASK, Offset 28h Slave Mode 24 Interrupt Mask Register IMASK, offset 28h Bits 15-3 Reserved -Write as 25 Specific End-of-Interrupt Register EOI, offset 22h Interrupt Vector Register INTVEC, Offset 20h Slave Mode Bits 15-8 Reserved -Read asBits 2-0 Reserved -Read as Interrupt Control Unit Timer Control Unit Timer Control Unit Register Summary OffsetfromTimer Control Unit Programmable Registers Timer Operating Frequency Bits 11-6 Reserved -Set to Timer Control Unit Timer 2 Mode and Control Register T2CON, Offset 66h Bits 12-6 Reserved -Set toBits 4-1 Reserved -Set to TC15-TC0 Value of these registers at reset is undefined Timer Control Unit DMA Controller DMA OperationDMA Controller Register Summary Offsetfrom DMA Controller 10-1 Programmable DMA Registers 10-2 DMA Controller DMA Control Registers D0CON, Offset CAh, D1CON, Offset DAh DMA Controller 10-3 Synchronization Type Sync Type10-4 DMA Controller DMA Transfer Count Registers D0TC, D1TC, offsets C8h and D8h DMA Controller 10-5 10-6 DMA Controller DMA Controller 10-7 10-8 DMA Controller DMA Controller 10-9 DMA Requests 10-10 DMA Controller Synchronization Timing Source Synchronization TimingDestination Synchronization Timing DMA Controller 10-11 DMA Acknowledge DMA PriorityDMA Programming 10-12 DMA Controller DMA Channels on Reset DMA Controller 10-13 10-14 DMA Controller Asynchronous Serial Port Asynchronous Serial Port Register Summary OffsetfromAsynchronous Serial Port 11-1 Serial Port Control Register SPCT, Offset 80h 11-2 Asynchronous Serial Port Parity Mode Bit Settings Asynchronous Serial Port 11-3 Serial Port Status Register SPSTS, Offset 82h Bits 15-7 Reserved -Set to11-4 Asynchronous Serial Port Serial Port Transmit Data Register SPTD, Offset 84h Bits 15-8 ReservedAsynchronous Serial Port 11-5 Serial Port Receive Data Register SPRD, Offset 86h 11-6 Asynchronous Serial Port Serial Port Baud Rate Divisor Register SPBAUD, Offset 88h Asynchronous Serial Port 11-7 11-8 Asynchronous Serial Port Synchronous Serial Interface Synchronous Serial Interface Register Summary Offset fromSynchronous Serial Interface 12-1 Four-Pin Interface 12-2 Synchronous Serial Interface Synchronous Serial Status Register SSS, Offset 10h Synchronous Serial Interface 12-3 Synchronous Serial Control Register SSC, Offset 12h Bits 15-6 Reserved -Set toBits 3-2 Reserved -Set to Bits 15-8 Reserved -Set to Synchronous Serial Interface 12-5 Synchronous Serial Receive Register SSR, Offset 18h 12-6 Synchronous Serial Interface SSI Programming Synchronous Serial Interface 12-7 Synchronous Serial Interface Multiple Write Synchronous Serial Interface Multiple Read Programmable I/O Pins Programmable I/O Pins 13-1 Registers PIOMODE1, 76h PDIR0, 78h PDATA0, 7Ah 13-2 PIO Mode Registers PIO Mode 1 Register PIOMODE1, Offset 76hPIO Mode 0 Register PIOMODE0, Offset 70h PIO Mode and PIO Direction Settings Pin Function PIO Direction Registers PIO Direction 1 Register PDIR1, Offset 78hPIO Direction 0 Register PDIR0, Offset 72h 13-4 Programmable I/O Pins 13-5 PIO Data RegistersPIO Data Register 1 PDATA1, Offset 7Ah PIO Data Register 0 PDATA0, Offset 74h 13-6 Register Summary Register Summary Rescon T1CMPB Figure A-1 Internal Register Summary Memory Partition Register Mdram DMA 0 Control Register D0CON Internal Memory Chip Select Register Imcs Serial Port Baud Rate Divisor Register Spbaud PMODE15-PMODE0 Timer 2 Maxcount Compare a Register T2CMPA Timer 0 Maxcount Compare B Register T0CMPB Sfnm Interrupt Request Register Reqst Master Mode Interrupt Request Register Reqst Slave Mode Interrupt Mask Register Imask Interrupt Vector Register Intvec Slave Mode Index Index Index Index Index Index Index Index Index Index Index