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AMD Am186TMER, Am188TMER 6.3 EMULATOR AND DEBUG MODES, 6.3.1 Internal Memory Disable, 6.3.2 Show Read Enable

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Internal Memory

6-2

6.3 EMULATOR AND DEBUG MODES

There are two debug modes associated with the internal memory. One mode allows users

to disable the internal RAM, and the other mode makes it possible to drive data on the

external data bus during internal RAM read cycles.

Normal operation of internal RAM has all control signals for reads and writes and data for

writes visible externally. Accesses to internal memory can be detected externally by

comparing the address on A19–A0 with the address space of the internal memory.

6.3.1 Internal Memory Disable

When this mode is activated, the internal RAM is disabled and all accesses into the internal

memory space are made externally for debugging purposes. This mode is activated by

pulling the S1/IMDIS pin Low during reset. To use this debug mode, internal memory space

must first be activated via the IMCS Register as described on page 6-3.

6.3.2 Show Read Enable

When this mode is activated, the data from the internal RAM read cycles are driven on the

AD15–AD0 bus. Note that if a byte read is being shown, the unused byte will also be driven

on the AD15–AD0 bus. This mode can be activated externally by pulling the S0/SREN pin

Low during reset or by setting the SR bit in the IMCS Register. If this feature is activated

externally using the SREN pin, the value of the SR bit is ignored. Many emulators assert

the SREN pin. For more details, see the IMCS Register information on page 6-3.

During an internal memory read with show read enabled, the address will be driven on th e

AD bus during t1 and t2. The data being read will be driven on the AD bus during t3 and t4

by the Am186ER or Am188ER microcontrollers. Special system care must be taken to

avoid bus contention, since normal reads have the AD bus three-stated during t2, t3, and

t4. It is best to ensure that no external device overlaps the internal memory space.

Contents

Main 1997 Advanced Micro Devices, Inc. All rights reserved. Trademarks IF YOU HAVE QUESTIONS, WERE HERE TO HELP YOU. Customer Service Hotline and World Wide Web Support Documentation and Literature Page TABLE OF CONTENTS Page Page Page LIST OF FIGURES Page LIST OF TABLES Page PREFACE INTRODUCTION AND OVERVIEW DESIGN PHILOSOPHY PURPOSE OF THIS MANUAL Am186 and Am188 Family Instruction Set Manual, INTENDED AUDIENCE AMD DOCUMENTATION E86 Microcontroller Family 1 1.1 KEY FEATURES AND BENEFITS 1.2 DISTINCTIVE CHARACTERISTICS Page Features and Performance 1-4 Figure 1-1 Am186ER Microcontroller Block Diagram Features and Performance 1-5 Figure 1-2 Am188ER Microcontroller Block Diagram 1.3 APPLICATION CONSIDERATIONS 1.3.1 Clock Generation 1.3.2 Memory Interface 1.3.3 Serial Communications Port Page 2 2.1 REGISTER SET Programming 2-2 Figure 2-1 Register Set 2.1.1 Processor Status Flags Register undefined Figure 2- 2 Processor Status Flags Register (FLAGS) 2.2 MEMORY ORGANIZATION AND ADDRESS GENERATION 2.3 I/O SPACE 2.4 INSTRUCTION SET The Am186 and Am188 Family Instruction Set Manual Page Page Page 2.5 SEGMENTS 2.6 DATA TYPES Programming 2-9 Figure 2-5 Supported Data Types 2.7 ADDRESSING MODES Register and Immediate Operands Memory Operands 3 3.1 PIN DESCRIPTIONS Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 3.1.1 Pins That Are Used by Emulators 3.2 BUS OPERATION System Overview 3-19 Figure 3-1 Am186ER Microcontroller Address BusNormal Read and Write Operation Figure 3-2 Am186ER MicrocontrollerRead and Write with Address Bus Disable In Effect System Overview 3-20 Figure 3-3 Am188ER Microcontroller Address BusNormal Read and Write Operation Figure 3-4 Am188ER MicrocontrollerRead and Write with Address Bus Disable In Effect 3.3 BUS INTERFACE UNIT Am186ER and Am188ER Microcontrollers Data Sheet 3.3.1 Nonmultiplexed Address Bus 3.3.2 Byte Write Enables 3.3.3 Pseudo Static RAM (PSRAM) Support Page 3.4 CLOCK AND POWER MANAGEMENT UNIT 3.4.1 Phase-Locked Loop (PLL) 3.4.2 Crystal-Driven Clock Source 3.4.3 External Source Clock 3.4.4 System Clocks 3.4.5 Power-Save Operation Page 4 4.1 OVERVIEW Peripheral Control Block 4-2 Figure 4-1 Peripheral Control Block Register Map Gaps in offset addresses indicate reserved registers. Changed from 80C186 microcontroller. Peripheral Control Block 4-3 Changed from 80C186 microcontroller. Gaps in offset addresses indicate reserved registers. 4.1.1 Peripheral Control Block Relocation Register (RELREG, Offset FEh) 4.1.2 Reset Configuration Register (RESCON, Offset F6h) 4.1.3 Processor Release Level Register (PRL, Of fset F4h) 4.1.4 Power-Save Control Register (PDCON, Offset F0h) 4.2 INITIALIZATION AND PROCESSOR RESET Note: Registers not listed in this table are undefined at reset. Page 5 5.1 OVERVIEW Note: The PCS4 chip select is not implemented on the Am186ER and Am188ER microcontrollers. A write will enable an external memory or peripheral chip select register. 5.2 CHIP SELECT TIMING 5.3 READY AND WAIT-STATE PROGRAMMING 5.4 CHIP SELECT OVERLAP 5.5 CHIP SELECT REGISTERS 5.5.1 Upper Memory Chip Select Register (UMCS, Offset A0h) Page 5.5.2 Low Memory Chip Select Register (LMCS, Offset A2h) Page 5.5.3 Midrange Memory Chip Select Register (MMCS, Offset A6h) Page 5.5.4 PCS and MCS Auxiliary Register (MPCS, Offset A8h) Page 5.5.5 Peripheral Chip Select Register (PACS, Offset A4h) Page Page 6 6.1 OVERVIEW not 6.2 INTERACTION WITH EXTERNAL RAM 6.3 EMULATOR AND DEBUG MODES 6.3.1 Internal Memory Disable 6.3.2 Show Read Enable 6.4 INTERNAL MEMORY CHIP SELECT REGISTER (IMCS, OFFSET ACh) Page 7 7.1 OVERVIEW 7.1.1 Memory Partition Register (MDRAM, Offset E0h) 7.1.2 Clock Prescaler Register (CDRAM, Offset E2h) 7.1.3 Enable RCU Register (EDRAM, Offset E4h) 8 8.1 OVERVIEW 8.1.1 Definitions of Interrupt Terms Overall Priority Page 8.1.2 Interrupt Conditions and Sequence 8.1.3 Interrupt Priority 8.1.4 Software Exceptions, Traps, and NMI Page 8.1.5 Interrupt Acknowledge 8.1.6 Interrupt Controller Reset Conditions 8.2 MASTER MODE OPERATION 8.2.1 Fully Nested Mode 8.2.2 Cascade Mode 8.2.3 Special Fully Nested Mode 8.2.4 Operation in a Polled Environment 8.2.5 End-of-Interrupt Write to the EOI Register 8.3 MASTER MODE INTERRUPT CONTROLLER REGISTERS 8.3.1 INT0 and INT1 Control Registers (I0CON, Offset 38h, I1CON, Offset 3Ah) Page 8.3.2 INT2 and INT3 Control Registers (I2CON, Offset 3Ch, I3CON, Offset 3Eh) 8.3.3 INT4 Control Register (I4CON, Offset 40h) Page 8.3.5 Watchdog Timer Interrupt Control Register (WDCON, Offset 42h) (Master Mode) Must 8.3.6 Serial Port Interrupt Control Register (SPICON, Offset 44h) 8.3.7 Interrupt Status Register (INTSTS, Offset 30h) 8.3.8 Interrupt Request Register (REQST, Offset 2Eh) 8.3.9 In-Service Register (INSERV, Offset 2Ch) 8.3.10 Priority Mask Register (PRIMSK, Offset 2Ah) 8.3.11 Interrupt Mask Register (IMASK, Offset 28h) 8.3.12 Poll Status Register (POLLST, Offset 26h) 8.3.13 Poll Register (POLL, Offset 24h) 8.3.14 End-of-Interrupt Register (EOI, Offset 22h) 8.4 SLAVE MODE OPERATION 8.4.1 Slave Mode Interrupt Nesting 8.4.2 Slave Mode Interrupt Controller Registers Page 8.4.4 Interrupt Status Register (INTSTS, Offset 30h) 8.4.5 Interrupt Request Register (REQST, Offset 2Eh) 8.4.6 In-Service Register (INSERV, Offset 2Ch) 8.4.7 Priority Mask Register (PRIMSK, Offset 2Ah) 8.4.8 Interrupt Mask Register (IMASK, Offset 28h) 8.4.9 Specific End-of-Interrupt Register (EOI, Offset 22h) 8.4.10 Interrupt Vector Register (INTVEC, Offset 20h) Page 9 9.1 OVERVIEW 9.2 PROGRAMMABLE REGISTERS 9.2.1 Timer Operating Frequency 9.2.2 Timer 0 and Timer 1 Mode and Control Registers (T0CON, Offset 56h, T1CON, Offset 5Eh) Page 9.2.3 Timer 2 Mode and Control Register (T2CON, Offset 66h) 9.2.4 Timer Count Registers (T0CNT, Offset 50h, T1CNT, Offset 58h, T2CNT, Offset 60h) Page Page 10 10.1 OVERVIEW 10.2 DMA OPERATION DMA Controller 10-2 Figure 10-1 DMA Unit Block Diagram 10.3 PROGRAMMABLE DMA REGISTERS 10.3.1 DMA Control Registers (D0CON, Offset CAh, D1CON, Offset DAh) Page Page Page Page 10.3.5 DMA Source Address High Register (High Order Bits) (D0SRCH, Offset C2h, D1SRCH, Offset D2h) Page 10.4 DMA REQUESTS 10.4.1 Synchronization Timing 10.4.2 DMA Acknowledge 10.4.3 DMA Priority 10.4.4 DMA Programming 10.4.5 DMA Channels on Reset Page 11 11.1 OVERVIEW 11.2 PROGRAMMABLE REGISTERS 11.2.1 Serial Port Control Register (SPCT, Offset 80h) Page 11.2.2 Serial Port Status Register (SPSTS, Offset 82h) 11.2.3 Serial Port Transmit Data Register (SPTD, Offset 84h) 11.2.4 Serial Port Receive Data Register (SPRD, Offset 86h) 11.2.5 Serial Port Baud Rate Divisor Register (SPBAUD, Offset 88h) phase Page 12 12.1 OVERVIEW 12.1.1 Four-Pin Interface 12.2 PROGRAMMABLE REGISTERS 12.2.1 Synchronous Serial Status Register (SSS, Offset 10h) 12.2.2 Synchronous Serial Control Register (SSC, Offset 12h) Page 12.2.4 Synchronous Serial Receive Register (SSR, Offset 18h) 12.3 SSI PROGRAMMING Synchronous Serial Interface 12-8 Figure 12-5 Synchronous Serial Interface Multiple Write Figure 12-6 Synchronous Serial Interface Multiple Read 13 13.1 OVERVIEW Page 13.2 PIO MODE REGISTERS 13.2.1 PIO Mode 1 Register (PIOMODE1, Offset 76h) 13.2.2 PIO Mode 0 Register (PIOMODE0, Offset 70h) 13.3 PIO DIRECTION REGISTERS Power-On Reset State 13.3.1 PIO Direction 1 Register (PDIR1, Offset 78h) 13.3.2 PIO Direction 0 Register (PDIR0, Offset 72h) 13.4 PIO DATA REGISTERS 13.4.1 PIO Data Register 1 (PDATA1, Offset 7Ah) 13.4.2 PIO Data Register 0 (PDATA0, Offset 74h) 13.5 OPEN-DRAIN OUTPUTS Page APPENDIX A Page Page A-4 Figure A-1 Internal Register Summary Register Summary A-5 A-6 Register Summary A-7 A-8 Register Summary A-9 A-10 Register Summary A-11 A-12 Register Summary A-13 A-14 Register Summary A-15 A-16 INDEX A B Page C D E F G H I K L M N O P Q R S T U W X Z