If CLKSEL2 is held Low during power-on reset, the processor enters Times One mode. See Table 3-4.

This pin is latched within three crystal clock cycles after the rising edge of RES. Note that clock selection must be stable four clock cycles prior to exiting reset (i.e., RES going High).

UZI/CLKSEL2 is three-stated during bus holds and ONCE mode.

Table 3-4

Clocking Modes

 

 

 

 

 

 

 

 

Clocking Mode

 

CLKSEL2

CLKSEL1

 

 

 

 

 

 

 

H

 

 

H

Times Four

 

 

 

 

 

 

 

H

 

 

L

Divide by Two

 

 

 

 

 

 

 

L

 

 

H

Times One

 

 

 

 

 

 

 

L

 

 

L

Reserved1

Notes:

1The Reserved clocking mode should not be used. Entering the Reserved clocking mode may cause unpredictable system behavior.

 

VCC

Power Supply (input)

 

 

 

 

 

 

These pins supply power (+3.3 V) to the microcontroller.

 

 

 

 

 

 

Write High Byte, Am186ER Microcontroller Only

WHB

 

 

 

 

 

 

(output, three-state, synchronous)

 

 

 

 

 

 

This pin and

 

 

 

indicate to the system which bytes of the data bus

 

 

 

 

 

 

WLB

 

 

 

 

 

 

(upper, lower, or both) participate in a write cycle. In 80C186 designs,

 

 

 

 

 

 

this information is provided by

 

 

 

the least-significant address bit

 

 

 

 

 

 

BHE,

 

 

 

 

 

 

(AD0), and by

 

However, by using

 

 

 

 

and

 

 

 

the standard

 

 

 

 

 

 

WR.

WHB

WLB,

 

 

 

 

 

 

system-interface logic and external address latch that were required

 

 

 

 

 

 

are eliminated.

 

 

 

 

 

 

 

 

 

 

 

is asserted with AD15–AD8.

 

 

 

is the logical OR of

 

 

 

and

 

 

 

 

 

 

WHB

WHB

BHE

 

 

 

 

 

 

 

 

 

During reset, this pin is a pullup. This pin is three-stated during

 

 

 

 

 

 

WR.

 

 

 

 

 

 

bus holds and ONCE mode.

 

 

 

 

 

Write Low Byte, Am186ER Microcontroller Only

 

WLB/WB

 

 

 

 

 

 

(output, three-state, synchronous)

 

 

 

 

 

 

Write Byte, Am188ER Microcontroller Only

 

 

 

 

 

 

(output, three-state, synchronous)

 

 

 

 

 

 

 

 

 

—This pin and WHB indicate to the system which bytes of the data

 

 

 

 

 

 

WLB

 

 

 

 

 

 

bus (upper, lower, or both) participate in a write cycle. In 80C186

 

 

 

 

 

 

designs, this information is provided by

 

the least-significant

 

 

 

 

 

 

BHE,

 

 

 

 

 

 

address bit (AD0), and by

 

However, by using

 

and

 

 

the

 

 

 

 

 

 

WR.

WHB

WLB,

 

 

 

 

 

 

standard system interface logic and external address latch that were

 

 

 

 

 

 

required are eliminated.

 

 

 

 

 

 

 

 

is asserted with AD7–AD0.

 

is the logical OR of AD0 and

 

 

 

 

 

 

 

 

WLB

WLB

WR.

 

 

 

 

 

 

This pin is three-stated during bus holds and ONCE mode.

 

 

 

 

 

 

 

—On the Am188ER microcontroller, this pin indicates a write to the

 

 

 

 

 

 

WB

 

 

 

 

 

 

bus.

 

 

uses the same early timing as the nonmultiplexed address

 

 

 

 

 

 

WB

 

 

 

 

 

 

bus.

 

is associated with AD7–AD0. This pin is three-stated during

 

 

 

 

 

 

WB

 

 

 

 

 

 

bus holds and ONCE mode.

3-16

System Overview

Page 48
Image 48
AMD Am186TMER Power Supply input, Write High Byte, Am186ER Microcontroller Only, Output, three-state, synchronous