AMD Am186TMER Clock Output a output, synchronous, Clock Output B output, synchronous, Ground

functionality in this instance. See Table 3-1 on page 3-10.)The pin is

sampled within three crystal clock cycles after the rising edge of

RES.

BHE/ADEN is three-stated during bus holds and ONCE mode.

See section 5.5.1 and section 5.5.2 for additional information on

enabling and disabling the AD bus during the address phase of a bus

cycle.

CLKOUTA

Clock Output A (output, synchronous)

This pin supplies the internal clock to the system. Depending on the

value of the Power-Save Control (PDCON) Register, CLKOUTA

operates at either the CPU fundamental clock frequency (which varies

with the Divide By Two, Times One, and Times Four clocking modes),

the power-save frequency, or is three-stated. CLKOUTA remains active

during reset and bus hold conditions.

CLKOUTB

Clock Output B (output, synchronous)

This pin supplies an additional clock to the system. Depending on the

value of the Power-Save Control (PDCON) Register, CLKOUTB

operates at either the CPU fundamental clock frequency (which varies

with the Divide By Two, Times One, and Times Four clocking modes),

the power-save frequency, or is three-stated. CLKOUTB remains active

during reset and bus hold conditions.

Data Enable (output, three-state, synchronous)

DEN

This pin supplies an output enable to an external data-bus transceiver.

is asserted during memory, I/O, and interrupt acknowledge cycles.

DEN

DEN

is deasserted when DT/R

changes state. DEN is three-stated

during a bus hold or reset condition.

DRQ1–DRQ0

DMA Requests (input, synchronous, level-sensitive)

These pins indicate to the microcontroller that an external device is

ready for DMA channel 1 or channel 0 to perform a transfer. DRQ1–

DRQ0 are level-triggered and internally synchronized.

The DRQ signals are not latched and must remain active until serviced.

Data Transmit or Receive (output, three-state, synchronous)

DT/R

This pin indicates which direction data should flow through an external

is asserted High, the microcontroller

data-bus transceiver. When DT/R

transmits data. When this pin is deasserted Low, the microcontroller

receives data. DT/R is three-stated during a bus hold or reset condition.

GND

Ground

These pins connect the system ground to the microcontroller.

HLDA

Bus Hold Acknowledge (output, synchronous)

When an external bus master requests control of the local bus (by

asserting HOLD), the microcontroller completes the bus cycle in

progress and then relinquishes control of the bus to the external bus

master by asserting HLDA and three-stating

DEN,

RD,

WR,

S2–S0,

AD15–AD0, S6, A19–A0,

and then driving

BHE,

WHB,

WLB,

and DT/R,

the chip selects

LCS,

UCS,

MCS3–MCS0, PCS6–PCS5, and PCS3–

High.

PCS0

3-4 System Overview