AMD Am186TMER, Am188TMER user manual Maskable Interrupt Request 2 input, asynchronous

INT2/INTA0	Maskable Interrupt Request 2 (input, asynchronous)
	Interrupt Acknowledge 0 (output, synchronous)
	INT2—This pin indicates to the microcontroller that an interrupt request
	has occurred. If the INT2 pin is not masked, the microcontroller transfers
	program execution to the location specified by the INT2 vector in the
	microcontroller interrupt vector table.
	Interrupt requests are synchronized internally and can be edge-
	triggered or level-triggered. To guarantee the interrupt is recognized,
	the device issuing the request must continue asserting INT2 until the
	request is acknowledged. INT2 becomes			when INT0 is
			INTA0
	configured in Cascade mode.
		—When the microcontroller interrupt control unit is operating in
	INTA0
	Cascade mode, this pin indicates to the system that the microcontroller
	needs an interrupt type to process the interrupt request on INT0. The
	peripheral issuing the interrupt request must provide the microcontroller
	with the corresponding interrupt type.
	Maskable Interrupt Request 3 (input, asynchronous)
INT3/INTA1/IRQ
	Interrupt Acknowledge 1 (output, synchronous)
	Slave Interrupt Request (output, synchronous)
	INT3—This pin indicates to the microcontroller that an interrupt request
	has occurred. If the INT3 pin is not masked, the microcontroller then
	transfers program execution to the location specified by the INT3 vector
	in the microcontroller interrupt vector table.
	Interrupt requests are synchronized internally and can be edge-
	triggered or level-triggered. To guarantee the interrupt is recognized,
	the device issuing the request must continue asserting INT3 until the
	request is acknowledged. INT3 becomes			when INT1 is
			INTA1
	configured in Cascade mode.
		—When the microcontroller interrupt control unit is operating in
	INTA1
	Cascade mode, this pin indicates to the system that the microcontroller
	needs an interrupt type to process the interrupt request on INT1. The
	peripheral issuing the interrupt request must provide the microcontroller
	with the corresponding interrupt type.
	IRQ—When the microcontroller interrupt control unit is operating as a
	slave to an external master interrupt controller, this pin lets the
	microcontroller issue an interrupt request to the external master
	interrupt controller.
INT4	Maskable Interrupt Request 4 (input, asynchronous)
	This pin indicates to the microcontroller that an interrupt request has
	occurred. If the INT4 pin is not masked, the microcontroller then
	transfers program execution to the location specified by the INT4 vector
	in the microcontroller interrupt vector table.
	Interrupt requests are synchronized internally and can be edge-
	triggered or level-triggered. To guarantee the interrupt is recognized,
	the device issuing the request must continue asserting INT4 until the
	request is acknowledged.

3-6 System Overview