AMD Am188TMER, Am186TMER user manual DMA Controller 10-9

10.3.6DMA Source Address Low Register

(Low Order Bits) (D0SRCL, Offset C0h, D1SRCL, Offset D0h)

Figure 10-7shows the DMA Source Address Low register. The sixteen bits of this register are combined with the four bits of the DMA Source Address High register (see Figure 10- 6) to produce a 20-bit source address.

Figure 10-7 DMA Source Address Low Register (D0SRCL, D1SRCL, offsets C0h and D0h)

15 7 0

DSA15–DSA0

The value of D0SRCL and D1SRCL at reset is undefined.

Bits 15–0: DMA Source Address Low (DSA15–DSA0) —These bits are driven onto

A15–A0 during the read phase of a DMA transfer.

DMA Controller 10-9