AMD Am188TMER, Am186TMER user manual Table of Contents

TABLE OF CONTENTS

PREFACE	INTRODUCTION AND OVERVIEW
	Design Philosophy	. xiii
	Purpose of this Manual	. xiii
	Intended Audience	. xiii
	User’s Manual Overview	. xiii
	AMD Documentation	. xiv
	E86™ Microcontroller Family	xiv

CHAPTER 1	FEATURES AND PERFORMANCE
	1.1	Key Features and Benefits		1-1
	1.2	Distinctive Characteristics		1-2
	1.3	Application Considerations		1-6
		1.3.1	Clock Generation	1-6
		1.3.2	Memory Interface	1-7
		1.3.3	Serial Communications Port	1-7
	1.4	Third-Party Development Support Products		1-8

CHAPTER 2	PROGRAMMING
	2.1	Register Set	. 2-1
		2.1.1 Processor Status Flags Register	. 2-2
	2.2	Memory Organization and Address Generation	. 2-3
	2.3	I/O Space	. 2-4
	2.4	Instruction Set	. 2-4
	2.5	Segments	. 2-8
	2.6	Data Types	. 2-8
	2.7	Addressing Modes	2-10

CHAPTER 3 SYSTEM OVERVIEW

3.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1 Pins That Are Used by Emulators . . . . . . . . . . . . . . . . . . . . . . . 3-17

3.2 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.3 Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

3.3.1 Nonmultiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

3.3.2 Byte Write Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

3.3.3 Pseudo Static RAM (PSRAM) Support . . . . . . . . . . . . . . . . . . . . 3-21

3.4 Clock and Power Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.4.1 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23

3.4.2 Crystal-Driven Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

3.4.3 External Source Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

3.4.4 System Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

3.4.5 Power-Save Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25

CHAPTER 4 PERIPHERAL CONTROL BLOCK

4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.1.1Peripheral Control Block Relocation Register

(RELREG, Offset FEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.1.2 Reset Configuration Register (RESCON, Offset F6h). . . . . . . . . . 4-5 4.1.3 Processor Release Level Register (PRL, Offset F4h) . . . . . . . . . . 4-6 4.1.4 Power-Save Control Register (PDCON, Offset F0h). . . . . . . . . . . 4-7

4.2 Initialization and Processor Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

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