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AMD Am188TMER, Am186TMER user manual Register Summary

Models: Am186TMER Am188TMER

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APPENDIX

A REGISTER SUMMARY

This appendix summarizes the peripheral control block registers. Table A-1 lists all the registers. Figure A-1shows the layout of each of the internal registers.

The column titled Comment in Table A-1 is used to identify the specific use of interrupt registers when there is a mix of master mode and slave mode usage. The registers that are marked as Slave & master can have different configurations for the different modes.

Register Summary

A-1

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AMD Am188TMER, Am186TMER user manual Register Summary

Contents

Am186äER and Am188äER Microcontrollers User’s Manual Advanced Micro Devices, Inc. All rights reserved Documentation and Literature Customer ServiceIf YOU have QUESTIONS, WE’RE Here to Help YOU Hotline and World Wide Web SupportPage Table of Contents Chip Select Unit Timer Control Unit Chapter DMA Controller Viii Table of ContentsPCS MCS List of FiguresFigure A-1 Processor Release Level PRL Register High-Order Byte Values List of TablesXii Table of Contents Intended Audience Introduction and OverviewDesign Philosophy Purpose of this ManualE86 Microcontroller Family AMD DocumentationFeatures and Performance KEY Features and BenefitsFeatures and Performance Distinctive Characteristics Features and Performance Am186ER Microcontroller Block Diagram Am188ER Microcontroller Block Diagram Clock Generation Application ConsiderationsSerial Communications Port Memory InterfaceTHIRD-PARTY Development Support Products Programming Register SETProgramming Bits 15-12 -Reserved Processor Status Flags RegisterBit 1 Reserved Memory Organization and Address GenerationBit 5 Reserved Bit 3 ReservedInstruction SET I/O SpaceMnemonic Instruction Name Instruction SetJB/JNAE OUT Segment Register Implicit Segment Selection Rule SegmentsData Types Segment Register Selection RulesSupported Data Types Memory Operands Memory Addressing Mode ExamplesAddressing Modes Register and Immediate OperandsA19-A0 Address Bus output, three-state, synchronous System OverviewPIN Descriptions Pin TerminologyAden Address Latch Enable output, synchronousThree-state, output, synchronous Bus High Enable, Am186ER Microcontroller OnlyAddress Enable, Am186ER Microcontroller Only Asynchronous Ready input, asynchronous, level-sensitiveDMA Requests input, synchronous, level-sensitive Data Enable output, three-state, synchronousClock Output a output, synchronous Clock Output B output, synchronousSlave Select input, asynchronous Bus Hold Request input, synchronous, level-sensitiveMaskable Interrupt Request 0 input, asynchronous Maskable Interrupt Request 1 input, asynchronousInterrupt Acknowledge 1 output, synchronous Maskable Interrupt Request 2 input, asynchronousInterrupt Acknowledge 0 output, synchronous Maskable Interrupt Request 3 input, asynchronousAutomatic Refresh output, synchronous Once Mode Request 0 inputMidrange Memory Chip Select Output, synchronous, internal pullupPeripheral Chip Select 6 output, synchronous Peripheral Chip Selects output, synchronousPeripheral Chip Select 5 output, synchronous Latched Address Bit 1 output, synchronousSystem Overview PIO Pin Assignments-Numeric Listing PIO No Associated Pin Power-On Reset StatusPIO Pin Assignments-Alphabetic Listing Associated Pin PIO No Power-On Reset StatusRefresh 2 three-state, output, synchronous Reset input, asynchronous, level-sensitiveAddress Enable input, internal pullup Read Strobe output, synchronous, three-stateBus Cycle Status Bit 6 output, synchronous Internal Memory Disable input, internal pullupShow Read Enable input, internal pullup Bus Cycle Status output, three-state, synchronousSerial Data input/output, synchronous Serial Data Enables output, synchronousTimer Input 0 input, synchronous, edge-sensitive Serial Clock output, synchronous, three-stateOnce Mode Request 1 input, internal pullup Timer Input 1 input, synchronous, edge-sensitiveTimer Output 0 output, synchronous Timer Output 1 output, synchronousWrite Low Byte, Am186ER Microcontroller Only Power Supply inputWrite High Byte, Am186ER Microcontroller Only Output, three-state, synchronousPins That Are Used by Emulators BUS Operation Clkouta A19-A0 Address AD7-AD0 Pseudo Static RAM Psram Support Byte Write EnablesBUS Interface Unit Nonmultiplexed Address BusSystem Overview Min Clock and Power Management UnitPhase-Locked Loop PLL Maximum and Minimum Clock Frequencies Mode X1/X2External Source Clock Crystal-Driven Clock SourceSystem Clocks Power-Save OperationSystem Overview Peripheral Control Block OverviewPeripheral Control Block Peripheral Control Block Register Map Timer 1 Count Register Bit 13 Reserved Bit 15 ReservedReset Configuration Register RESCON, offset F6h Reset Configuration Register RESCON, Offset F6hBits 7-0 Reserved -Value is undefined Processor Release Level Register PRL, Offset F4hBits 7-3 Reserved -Read back as Power-Save Control Register PDCON, Offset F0hDivider Factor Initialization and Processor ResetRegisters not listed in this table are undefined at reset Peripheral Control Block Chip Select Unit Chip Select UnitChip Select Timing Ready and WAIT-STATE ProgrammingChip Select Overlap Chip Select Registers Memory Block Starting Upper Memory Chip Select Register UMCS, Offset A0hBit 15 Reserved-Set to Umcs Block Size Programming ValuesBits 6 Reserved- Set to Bits 5-3 Reserved- Set to Bits 11-8 ReservedLow Memory Chip Select Register LMCS, Offset A2h Lmcs Block Size Programming ValuesMemory Block Ending Bits 11-8 Reserved- Set to Midrange Memory Chip Select Register MMCS, offset A6h Midrange Memory Chip Select Register MMCS, Offset A6hBits 8-3 Reserved -Set to Total Block Individual PCS and MCS Auxiliary Register MPCS, Offset A8hBit 15 Reserved- Set to MCS Block Size ProgrammingBits 5-3 Reserved -Set to Peripheral Chip Select Register PACS, offset A4h Peripheral Chip Select Register PACS, Offset A4hPCS3-PCS0 Wait-State Encoding Wait States Bits 6-4 Reserved -Set toPCS Address Ranges Line Low HighChip Select Unit Internal Memory Interaction with External RAMInternal Memory Internal Memory Disable Show Read EnableEmulator and Debug Modes Bits 8-0 Reserved -Set to Internal Memory Chip Select Register IMCS, Offset AChInternal Memory Refresh Control Unit Refresh Control UnitMemory Partition Register MDRAM, Offset E0h Bits 8-0 Reserved -Read back asEnable RCU Register EDRAM, Offset E4h Clock Prescaler Register CDRAM, Offset E2hBits 14-9 Reserved -Read back as Interrupt Vector Table Interrupt Control UnitDefinitions of Interrupt Terms Interrupt TypeInterrupt Priority Interrupt Enable Flag ifMaskable and Nonmaskable Interrupts Interrupt Mask BitSoftware Exceptions Am186ER and Am188ER Microcontroller Interrupt TypesOverall Interrupt Conditions and Sequence Interrupt Priority Nonmaskable Interrupts and Software Interrupt PriorityMaskable Hardware Interrupt Priority Nonmaskable Interrupt-NMI Interrupt Type 02h Divide Error Exception Interrupt Type 00hSoftware Exceptions, Traps, and NMI Trace Interrupt Interrupt Type 01hUnused Opcode Exception Interrupt Type 06h Breakpoint Interrupt Interrupt Type 03hInto Detected Overflow Exception Interrupt Type 04h Array Bounds Exception Interrupt Type 05hExternal Interrupt Acknowledge Bus Cycles Interrupt AcknowledgeInterrupt Controller Reset Conditions Fully Nested Mode Master Mode OperationCascade Mode Interrupt Controller Connections Cascade ModeSpecial Fully Nested Mode Operation in a Polled EnvironmentEnd-of-Interrupt Write to the EOI Register Master Mode Interrupt Controller Registers Value of I0CON and I1CON at reset is 000Fh Priority Level Bits 15-5 Reserved -Set to INT4 Control Register I4CON, offset 40h 3 INT4 Control Register I4CON, Offset 40h Master ModeBits 15-4 Reserved -Set to Value of Wdcon at reset is 000Fh Serial Port Interrupt Control Register SPICON, offset 44h Bits 15-5 Reserved -Set to Bit 4 Reserved-Set to10 Interrupt Status Register INTSTS, offset 30h Interrupt Status Register INTSTS, Offset 30h Master ModeBits 15-11 Reserved Interrupt Request Register REQST, Offset 2Eh Master Mode12 In-Service Register INSERV, offset 2Ch In-Service Register INSERV, Offset 2Ch Master ModePriority Field Mask Master Mode PR2-PR0 Priority Mask Register PRIMSK, Offset 2Ah Master Mode14 Interrupt Mask Register IMASK, offset 28h Interrupt Mask Register IMASK, Offset 28h Master ModeBits 14-5 Reserved -Set to Poll Status Register POLLST, Offset 26h Master Mode16 Poll Register POLL, offset 24h Poll Register POLL, Offset 24h Master ModeBits 14-5 Reserved End-of-Interrupt Register EOI, Offset 22h Master ModeSlave Mode Operation Slave Mode Interrupt NestingSlave Mode Interrupt Controller Registers These registers are set to 000Fh on reset 20 Interrupt Status Register INTSTS, offset 30h Interrupt Status Register INTSTS, Offset 30h Slave Mode21 Interrupt Request Register REQST, offset 2Eh Interrupt Request Register REQST, Offset 2Eh Slave Mode22 In-Service Register INSERV, offset 2Ch In-Service Register INSERV, Offset 2Ch Slave ModePriority Field Mask Slave Mode PR2-PR0 Priority Mask Register PRIMSK, Offset 2Ah Slave Mode24 Interrupt Mask Register IMASK, offset 28h Interrupt Mask Register IMASK, Offset 28h Slave Mode25 Specific End-of-Interrupt Register EOI, offset 22h Bits 15-3 Reserved -Write asInterrupt Vector Register INTVEC, Offset 20h Slave Mode Bits 15-8 Reserved -Read asBits 2-0 Reserved -Read as Interrupt Control Unit Programmable Registers Timer Control UnitTimer Control Unit Register Summary Offsetfrom Timer Control UnitTimer Operating Frequency Bits 11-6 Reserved -Set to Timer Control Unit Timer 2 Mode and Control Register T2CON, Offset 66h Bits 12-6 Reserved -Set toBits 4-1 Reserved -Set to TC15-TC0 Value of these registers at reset is undefined Timer Control Unit DMA Controller 10-1 DMA ControllerDMA Operation DMA Controller Register Summary Offsetfrom10-2 DMA Controller Programmable DMA RegistersDMA Controller 10-3 DMA Control Registers D0CON, Offset CAh, D1CON, Offset DAhSynchronization Type Sync Type10-4 DMA Controller DMA Controller 10-5 DMA Transfer Count Registers D0TC, D1TC, offsets C8h and D8h10-6 DMA Controller DMA Controller 10-7 10-8 DMA Controller DMA Controller 10-9 10-10 DMA Controller DMA RequestsDMA Controller 10-11 Synchronization TimingSource Synchronization Timing Destination Synchronization Timing10-12 DMA Controller DMA AcknowledgeDMA Priority DMA ProgrammingDMA Controller 10-13 DMA Channels on Reset10-14 DMA Controller Asynchronous Serial Port Asynchronous Serial Port Register Summary OffsetfromAsynchronous Serial Port 11-1 11-2 Asynchronous Serial Port Serial Port Control Register SPCT, Offset 80hAsynchronous Serial Port 11-3 Parity Mode Bit SettingsSerial Port Status Register SPSTS, Offset 82h Bits 15-7 Reserved -Set to11-4 Asynchronous Serial Port Serial Port Transmit Data Register SPTD, Offset 84h Bits 15-8 ReservedAsynchronous Serial Port 11-5 11-6 Asynchronous Serial Port Serial Port Receive Data Register SPRD, Offset 86hAsynchronous Serial Port 11-7 Serial Port Baud Rate Divisor Register SPBAUD, Offset 88h11-8 Asynchronous Serial Port Synchronous Serial Interface Synchronous Serial Interface Register Summary Offset fromSynchronous Serial Interface 12-1 12-2 Synchronous Serial Interface Four-Pin InterfaceSynchronous Serial Interface 12-3 Synchronous Serial Status Register SSS, Offset 10hSynchronous Serial Control Register SSC, Offset 12h Bits 15-6 Reserved -Set toBits 3-2 Reserved -Set to Synchronous Serial Interface 12-5 Bits 15-8 Reserved -Set to12-6 Synchronous Serial Interface Synchronous Serial Receive Register SSR, Offset 18hSynchronous Serial Interface 12-7 SSI ProgrammingSynchronous Serial Interface Multiple Read Synchronous Serial Interface Multiple WriteProgrammable I/O Pins 13-1 Programmable I/O Pins13-2 Registers PIOMODE1, 76h PDIR0, 78h PDATA0, 7AhPIO Mode and PIO Direction Settings Pin Function PIO Mode RegistersPIO Mode 1 Register PIOMODE1, Offset 76h PIO Mode 0 Register PIOMODE0, Offset 70h13-4 PIO Direction RegistersPIO Direction 1 Register PDIR1, Offset 78h PIO Direction 0 Register PDIR0, Offset 72hPIO Data Register 0 PDATA0, Offset 74h Programmable I/O Pins 13-5PIO Data Registers PIO Data Register 1 PDATA1, Offset 7Ah13-6 Register Summary Register SummaryRescon T1CMPB Figure A-1 Internal Register Summary Memory Partition Register Mdram DMA 0 Control Register D0CON Internal Memory Chip Select Register Imcs Serial Port Baud Rate Divisor Register Spbaud PMODE15-PMODE0 Timer 2 Maxcount Compare a Register T2CMPA Timer 0 Maxcount Compare B Register T0CMPB Sfnm Interrupt Request Register Reqst Master Mode Interrupt Request Register Reqst Slave Mode Interrupt Mask Register Imask Interrupt Vector Register Intvec Slave Mode Index IndexIndex Index Index Index Index Index Index Index Index