AMD Am186TMER Read Strobe output, synchronous, three-state, Address Enable input, internal pullup

RD

Read Strobe (output, synchronous, three-state)

—This pin indicates to the system that the microcontroller is

RD

performing a memory or I/O read cycle.

RD

is guaranteed not to be

asserted before the address and data bus is three-stated during the

address-to-data transition.

is three-stated during bus holds and

RD

ONCE mode.

Reset (input, asynchronous, level-sensitive)

RES

This pin causes the microcontroller to perform a reset. When

is

RES

asserted, the microcontroller immediately terminates its present activity,

clears its internal logic, and CPU control is transferred to the reset

address FFFF0h.

must be held Low for at least 1 ms. The assertion of

can be

RES

RES

asynchronous to CLKOUTA because

is synchronized internally.

RES

For proper initialization, VCC must be within specifications, and

CLKOUTA must be stable for more than four CLKOUTA periods during

which

RES

is asserted.

The microcontroller begins fetching instructions approximately

6.5CLKOUTA periods after RES is deasserted. This input is provided with a Schmitt trigger to facilitate power-on RES generation via an RC network.

RFSH2/ADEN

Refresh 2 (three-state, output, synchronous)

Address Enable (input, internal pullup)

—Available on the Am188ER microcontroller only,

2/

RFSH2

RFSH

is asserted Low to signify a DRAM refresh bus cycle. The use

ADEN

of

RFSH2/ADEN to signal a refresh is not valid when PSRAM mode is

signal is provided to the PSRAM.

selected. Instead, the MCS3/RFSH

During reset, this pin is a pullup. This pin is three-stated during bus

holds and ONCE mode.

—If

is held High or left floating on power-on reset,

ADEN

RFSH

2/ADEN

the AD bus (AO15–AO8 and AD7–AD0) is enabled or disabled during

the address portion of LCS and

bus cycles based on the DA bit in

UCS

the LMCS and UMCS registers. If the DA bit is set, the memory address

is accessed on the A19–A0 pins. This mode of operation reduces power

consumption. There is a weak internal pullup resistor on

RFSH2/ADEN,

so no external pullup is required.

If

RFSH2/ADEN is held Low on power-on reset, the AD bus drives both

addresses and data. (S6 and UZI also assume their normal functionality

in this instance. See Table 3-1 on page 3-10.)The pin is sampled within

three crystal clock cycles after the rising edge of

RES.

RFSH2/ADEN is

three-stated during bus holds and ONCE mode.

See section 5.5.1 and section 5.5.2 for additional information on

enabling and disabling the AD bus during the address phase of a bus

cycle.

RXD

Receive Data (input, asynchronous)

This pin supplies asynchronous serial receive data from the system to

the internal UART of the microcontroller.

3-12 System Overview