126 AMD Geodeā„¢ LX Processors Data Book
CPU Core Register Descriptions
33234H
5.5.2.17 XC History MSR (XC_HIST_MSR)
MSR Address 00001212h
Type RO
Reset Value 00000000_00000000h
XC_HIST_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD TYPE11 TYPE10 TYPE9 TYPE8 TYPE7 TYPE6
313029282726252423222120191817161514131211109876543210
RSVD TYPE5 TYPE4 TYPE3 TYPE2 TYPE1 TYPE0
XC_HIST_MSR Bit Descriptions
Bit Name Description (Note 1)
63:62 RSVD Reserved.
61:57 TYPE11 Exception Type 11.
56:52 TYPE10 Exception Type 10.
51:47 TYPE9 Exception Type 9.
46:42 TYPE8 Exception Type 8.
41:37 TYPE7 Exception Type 7.
36:32 TYPE6 Exception Type 6.
31:30 RSVD Reserved.
29:25 TYPE5 Exception Type 5.
24:20 TYPE4 Exception Type 4.
19:15 TYPE3 Exception Type 3.
14:10 TYPE2 Exception Type 2.
9:5 TYPE1 Exception Type 1.
4:0 TYPE0 Exception Type 0.
Note 1. Table 5-14 shows the definition of the types in the XC_HIST MSR.
Table 5-14. XC_HIST_MSR Exception Types
Value Description Value Description Value Description
00h Divide error 0Bh Segment not present 16h External system management
during I/O instruction
01h Debug 0Ch Stack fault 17h External system management
02h External non-maskable interrupt 0Dh General protection fault 18h Init
03h Breakpoint 0Eh Page fault 19h Reset
04h Overflow 0Fh Reserved 1Ah Internal suspend/stall
05h Bound 10h FPU error trap 1Bh External suspend/stall
06h Invalid operation code 11h Alignment fault 1Ch Unsuspend/unstall
07h FPU unavailable 12h FPU error interrupt 1Dh Triple fault shutdown
08h Double fault 13h Internal debug management 1Eh External maskable interrupt
09h Self-modified code fault 14h External debug management 1Fh No exception
0Ah Invalid task-state segment 15h I/O-initiated system management -- --