Main
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Contents
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List of Figures
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List of Tables
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1.0Overview
1.1 General Description
SDCLKs
Figure 1-1. Int ernal Block Diagram
1.2 Features
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2.0Architecture Overview
2.1 CPU Core
2.1.1 Integer Unit
2.1.2 Memory Management Unit
2.1.3 Cache and TLB Subsystem
2.2 GeodeLink Control Processor
2.3 GeodeLink Interface Units
2.4 GeodeLink Memory Controller
2.5 Graphics Processor
Table 2-1. Graphics Processor Feature Comparison
2.6 Display Controller
2.7 Video Processor
2.7.1 CRT Interface
2.7.2 TFT Controller
2.7.3 Video Output Port
2.10 Security Block
Page
3.0Signal Definitions
Figure 3-1. Signal Groups
AMD Geode
LX Processor
Table 3-1. Video Signal Definitions Per Mode
3.1 Buffer Types
Table 3-2. Buffer Type Characteristics
3.2 Bootstrap Options
3.3 Ball Assignments
Table 3-3. Bootstrap Options
Table 3-4. Ball Type Definitions
AMD Geode LX Processors Data Book 25
AMD Geode LX Processor
= GND Ball = PWR Ball = Strap Option Ball = Multiplexed Ball
(Top View)
26 AMD Geode LX Processors Data Book
Signal Definitions
Table 3-5. Ball Assignments - Sorted by Ball Number
Page
28 AMD Geode LX Processors Data Book
Signal Definitions
Page
Table 3-6. Ball Assignments - Sorted Alphabetically by Signal Name
Page
Table 3-6. Ball Assignments - Sorted Alphabet ically by Signal Name (Continued)
3.4 Signal Descriptions
3.4.1 System Interface Signals
3.4.1 System Interface Signals (Continued)
3.4.2 PLL Interface Signals
3.4.3 Memory Interface Signals (DDR)
3.4.3 Memory Interface Signals (DDR) (Continued)
3.4.4 Internal Test and Measurement Interface Signals
3.4.5 PCI Interface Signals
Page
3.4.5 PCI Interface Signals (Continued)
3.4.6 TFT Display Interface Signals
3.4.7 CRT Display Interface Signals
3.4.8 VIP Interface Signals
3.4.9 Power and Ground Interface Signals
Table 3-7. Signal Behavior During and After Reset
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4.0GeodeLink Interface Unit
4.1 MSR Set
Table 4-1. MSR Addressing
4.1.1 Port Address
Figure 4-1. GeodeLink Architecture
4.1.2 Port Addressing Exceptions
4.1.3 Memory and I/O Mapping
Table 4-2. MSR Mapping
Table 4-3. GLIU Memory Descriptor Address Hit and Routing Description
Table 4-4. GLIU I/O Descriptor Address Hit and Routing Description
4.2 GLIU Register Descriptions
Table 4-6. GLIU Specific MSRs Summary
Table 4-6. GLIU Specific MSRs Summary (Continued)
Table 4-7. GLIU Statistic and Comparator MSRs Summary
Page
Table 4-7. GLIU Statistic and Comparator MSRs Summary (Continued)
Table 4-8. GLIU P2D Descriptor MSRs Summary
Table 4-9. GLIU Reserved MSRs Summary
Table 4-10. GLIU IOD Descriptor MSRs Summary
4.2.1 Standard GeodeLink Device (GLD) MSRs
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4.2.2 GLIU Specific Registers
COH Register Map
COH Bit Descriptions
PAE Register Map
PAE Bit Descriptions
ARB Register Map
ARB Bit Descriptions
ASMI Register Map
ASMI Bit Descriptions
AERR Register Map
AERR Bit Descriptions
PHY_CAP Register Map
PHY_CAP Bit Descriptions
NOUT_RESP Register Map
NOUT_RESP Bit Descriptions
NOUT_WDATA Register Map
NOUT_WDATA Bit Descriptions
SLAVE_ONLY Register Map
SLAVE_ONLY Bit Descriptions
SLAVE_ONLY Bit Descriptions (Continued)
WHO AM I Register Map
WHO AM I Bit Descriptions
GLIU_SLV Register Map
GLIU_SLV Bit Descriptions
ARB2 Register Map
ARB2 Bit Descriptions
4.2.3 GLIU Statistic and Comparator MSRs
STATISTIC_CNT[0:3] Registers Map
STATISTIC_CNT[0:3] Bit Descriptions
STATISTIC_MASK[0:3] Register Map
STATISTIC_MASK[0:3] Bit Descriptions
STATISTIC_ACTION[0:3] Register Map
STATISTIC_ACTION[0:3] Bit Descriptions
RQ_COMPARE_VAL[0:3] Register
RQ_COMPARE_VAL[0:3] Bit Descriptions
RQ_COMPARE_MASK[0:3] Register Map
RQ_COMPARE_MASK[0:3] Bit Descriptions
DA_COMPARE_VAL_LO[0:3] Register
DA_COMPARE_VAL_LO[0:3] Bit Descriptions
DA_COMPARE_VAL_HI[0:3] Register Map
DA_COMPARE_VAL_HI[0:3] Bit Descriptions
DA_COMPARE_VAL_HI[0:3] Register Map
DA_COMPARE_MASK_LO[0:3] Bit Descriptions
DA_COMPARE_MASK_HI[0:3] Register Map
DA_COMPARE_MASK_HI[0:3] Bit Descriptions
4.2.4 P2D Descriptor Registers
P2D_BM Register Map
P2D_BM Bit Descriptions
P2D_BMO Register Map
P2D_BMO Bit Descriptions
P2D_R Register Map
P2D_R Bit Descriptions
P2D_RO Register Map
P2D_RO Bit Descriptions
P2D_SC Register Map
P2D_SC Bit Descriptions
Page
4.2.6 I/O Descriptors
IOD_BM[x] Register Map
IOD_BM[x] Bit Descriptions
IOD_SC[x] Register Map
IOD_SC[x] Bit Descriptions
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5.0CPU Core
5.1 Core Processor Initialization
Table 5-1. Initialized Core Register Controls
5.2 Instruction Set Overview
5.2.1 Lock Prefix
5.2.2 Register Sets
5.3 Application Register Set
Table 5-2. Application Register Set
5.3.1 General Purpose Registers
5.3.2 Segment Registers
5.3.3 Instruction Pointer Register
Table 5-3. Segment Register Selection Rules
5.3.4 EFLAGS Register
Table 5-4. EFLAGS Register
5.4 System Register Set
Table 5-5. System Register Set
5.4.1 Control Registers
Table 5-6. Control Registers Map
Table 5-7. CR4 Bit Descriptions
Table 5-8. CR3 Bit Descriptions
Table 5-9. CR2 Bit Descriptions
Table 5-10. CR0 Bit Descriptions
Table 5-10. CR0 Bit Descriptions (Continued)
Table 5-11. Effects of Various Combinations of EM, TS, and MP Bits
5.5 CPU Core Register Descriptions
Table 5-12. Standard GeodeLink Device MSRs Summary
Table 5-13. CPU Core Specific MSRs Summary
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5.5.1 Standard GeodeLink Device MSRs
Page
5.5.2 CPU Core Specific MSRs
TSC_MSR Register Map
TSC_MSR Bit Descriptions
PERF_CNT0_MSR Register Map
PERF_CNT0_MSR Bit Descriptions
PERF_CNT1_MSR Register Map
PERF_CNT1_MSR Bit Descriptions
SYS_CS_MSR Register Map
SYS_CS_MSR Bit Descriptions
SYS_SP_MSR Register Map
SYS_SP_MSR Bit Descriptions
SYS_IP_MSR Register Map
SYS_IP_MSR Bit Descriptions
PERF_SEL0_MSR Register Map
PERF_SEL0_MSR Bit Descriptions
PERF_SEL1_MSR Register Map
PERF_SEL1_MSR Bit Descriptions
IF_CONFIG_MSR Register Map
IF_CONFIG_MSR Bit Descriptions
Page
IF_CONFIG_MSR Bit Descriptions (Continued)
IF_INVALIDATE_MSR Register Map
IF_INVALIDATE_MSR Bit Descriptions
IF_TEST_ADDR_MSR Register Map
IF_TEST_ADDR_MSR Bit Descriptions
IF_TEST_ADDR_MSR Bit Descriptions (Continued)
IF_TEST_DATA_MSR Register Map for Target RAMs
IF_TEST_DATA_MSR Bit Descriptions for Target RAMs
IF_TEST_DATA_MSR Register Map for Tag RAMs
IF_TEST_DATA_MSR Bit Descriptions for Tag RAMs
IF_TEST_DATA_MSR Register Map for Level-0 COF Cache Tag
IF_TEST_DATA_MSR Bit Descriptions for Level-0 COF Cache Tag
Page
IF_TEST_DATA_MSR Register Map for Return Stack Valids
IF_TEST_DATA_MSR Bit Descriptions for Return Stack Valids
IF_SEQCOUNT_MSR Register Map
IF_SEQCOUNT_MSR Bit Descriptions
IF_BIST_MSR Register Map
IF_BIST_MSR Bit Descriptions
XC_CONFIG_MSR Register Map
XC_CONFIG_MSR Bit Descriptions
XC_MODE_MSR Register Map
XC_MODE_MSR Bit Descriptions
XC_HIST_MSR Register Map
XC_HIST_MSR Bit Descriptions
Table 5-14. XC_HIST_MSR Exception Types
XC_UADDR_MSR Register Map
XC_UADDR_MSR Bit Descriptions
ID_CONFIG_MSR Register Map
ID_CONFIG_MSR Bit Descriptions
SMM_CTL_MSR Register Map
SMM_CTL_MSR Bit Descriptions
DMI Control Register Map
DMI Control Register Bit Descriptions
DMI Control Register Bit Descriptions (Continued)
TEMPx_MSR Register Map
TEMPx_MSR Bit Descriptions
Segment Selector/Flags MSR Register Map
Segment Selector/Flags MSR Bit Descriptions
SMM_HDR_MSR Register Map
Segment Selector/Flags MSR Bit Descriptions (Continued)
SMM_HDR_MSR Bit Descriptions
DMM_HDR_MSR Register Map
DMM_HDR_MSR Bit Descriptions
Segment Base/Limit MSR Register Map
Segment Base/Limit MSR Bit Descriptions
DR1_DR0_MSR Register Map
DR1_DR0_MSR Bit Descriptions
DR3_DR2_MSR Register Map
DR2_DR3_MSR Bit Descriptions
DR7_DR6_MSR Register Map
DR7_DR6_MSR Bit Descriptions
XDR1_XDR0_MSR Register Map
XDR1_XDR0_MSR Bit Descriptions
XDR3_XDR2_MSR Register Map
XDR3_XDR2_MSR Bit Descriptions
XDR5_XDR4_MSR Register Map
XDR5_XDR4_MSR Bit Descriptions
XDR7_XDR6_MSR Register Map
XDR7_XDR6_MSR Bit Descriptions
XDR9_XDR8_MSR Register Map
XDR9_XDR8_MSR Bit Descriptions
XDR11_XDR10_MSR Register Map
XDR11_XDR10_MSR Bit Descriptions
EX_IP_MSR Register Map
EX_IP_MSR Bit Descriptions
WB_IP_MSR Register Map
WB_IP_MSR Bit Descriptions
EX_LIP_MSR Register Map
EX_LIP_MSR Bit Descriptions
WB_LIP_MSR Register Map
WB_LIP_MSR Bit Descriptions
C1_C0_LIP_MSR Register Map
C1_C0_LIP_MSR Bit Descriptions
C3_C2_LIP_MSR Register Map
C3_C2_LIP_MSR Bit Descriptions
FPENV_CS_MSR Register Map
FPENV_CS_MSR Bit Descriptions
FPENV_IP_MSR Register Map
FPENV_IP_MSR Bit Descriptions
FPENV_DS_MSR Register Map
FPENV_DS_MSR Bit Descriptions
FPENV_DP_MSR Register Map
FPENV_DP_MSR Bit Descriptions
FPENV_OP_MSR Register Map
FPENV_OP_MSR Bit Descriptions
AC_CONFIG_MSR Register Map
AC_CONFIG_MSR Bit Descriptions
General Registers MSRs Register Map
General Registers MSRs Bit Descriptions
EFLAG_MSR Register Map
EFLAG_MSR Bit Descriptions
IM_CONFIG_MSR Register Map
IM_CONFIG_MSR Bit Descriptions
IM_CONFIG_MSR Bit Descriptions (Continued)
IC_INDEX_MSR Register Map
IC_INDEX_MSR Bit Descriptions
IC_DATA_MSR Register Map
IC_DATA_MSR Bit Descriptions
IC_TAG_MSR MSR Register Map
IC_TAG_MSR Bit Descriptions
IC_TAG_I_MSR Register Map
IC_TAG_I_MSR Bit Descriptions
L0_IC_DATA_MSR Register Map
L0_IC_DATA_MSR Bit Descriptions
L0_IC_TAG_I_MSR Register Map
L0_IC_TAG_I_MSR Bit Descriptions
ITB_INDEX_MSR Register Map
ITB_INDEX_MSR Bit Descriptions
ITB_LRU_MSR Register Map
ITB_LRU_MSR Bit Descriptions
ITB_ENTRY_MSR, ITB_ENTRY_I_MSR, ITB_L0_ENTRY_MSR Register Map
ITB_ENTRY_MSR, ITB_ENTRY_I_MSR, ITB_L0_ENTRY_MSR Bit Descriptions
IM_BIST_TAG_MSR Register Map
IM_BIST_TAG_MSR Bit Descriptions
IM_BIST_DATA_MSR Register Map
IM_BIST_DATA_MSR Bit Descriptions
5.5.2.63 Data Memory Subsystem Configuration 0 MSR (DM_CONFIG0_MSR)
DM_CONFIG0_MSR Register Map
DM_CONFIG0_MSR Bit Descriptions
Page
DM_CONFIG0_MSR Bit Descriptions (Continued)
5.5.2.64 Data Memory Subsystem Configuration 1 MSR (DM_CONFIG1_MSR)
DM_CONFIG1_MSR Register Map
DM_CONFIG1_MSR Bit Descriptions
DM_CONFIG1_MSR Bit Descriptions (Continued)
DM_PFLOCK_MSR Register Map
DM_PFLOCK_MSR Bit Descriptions
RCONF_DEFAULT_MSR Register Map
RCONF_DEFAULT_MSR Bit Descriptions
RCONF_BYPASS_MSR Register Map
RCONF_BYPASS_MSR Bit Descriptions
RCONF_A0_BF_MSR Register Map
RCONF_A0_BF_MSR Bit Descriptions
RCONF_C0_DF_MSR Register Map
RCONF_C0_DF_MSR Bit Descriptions
RCONF_E0_FF_MSR Register Map
RCONF_E0_FF_MSR Bit Descriptions
RCONF_SMM_MSR Register Map
RCONF_SMM_MSR Bit Descriptions
RCONF_DMM_MSR Register Map
RCONF_DMM_MSR Register Bit Descriptions
RCONFx_MSR Register Map
RCONFx_MSR Bit Descriptions
Table 5-15. Region Properties Register Map
Table 5-16. Read Operations vs. Region Properties
Table 5-17. Write Operations vs. Region Properties
Table 5-17. Write Operations vs. Region Properties (Continued)
DC_INDEX_MSR Register Map
DC_INDEX_MSR Bit Descriptions
DC_DATA_MSR Register Map
DC_DATA_MSR Bit Descriptions
DC_TAG_MSR Register Map
DC_TAG_MSR Bit Descriptions
DC_TAG_MSR Bit Descriptions (Continued)
DC_TAG_I_MSR Register Map
SNOOP_MSR Register Map
SNOOP_MSR Bit Descriptions
L1DTLB_INDEX_MSR Register Map
L1DTLB_INDEX_MSR Bit Descriptions
L1DTLB_LRU_MSR Register Map
L1DTLB_LRU_MSR Bit Descriptions
L1DTLB_ENTRY_MSR Register Map
L1DTLB_ENTRY_MSR Bit Descriptions
L1DTLB_ENTRY_I_MSR Register Map
L2TLB_INDEX_MSR Register Map
L2TLB_INDEX_MSR Bit Descriptions
L2TLB_INDEX_MSR Bit Descriptions (Continued)
L2TLB_LRU_MSR Register Map
L2TLB_LRU_MSR Bit Descriptions
L2TLB_LRU_MSR Bit Descriptions (Continued)
L2TLB_ENTRY_MSR Register Map
L2TLB_ENTRY_MSR Bit Descriptions
L2TLB_ENTRY_MSR Bit Descriptions (Continued)
L2TLB_ENTRY_I_MSR Register Map
DM_BIST_MSR Register Map
DM_BIST_MSR Bit Descriptions
BC_CONFIG0_MSR Register Map
BC_CONFIG0_MSR Bit Descriptions
BC_CONFIG0_MSR Bit Descriptions (Continued)
RSVD_STS_MSR Bit Descriptions
MSR_LOCK_MSR Register Map
MSR_LOCK_MSR Bit Descriptions
RTSC_MSR Register Map
RTSC_MSR Bit Descriptions
RTSC_TSC_MSR Register Map
RTSC_TSC_MSR Bit Descriptions
L2_CONFIG_MSR Register Map
L2_CONFIG_MSR Bit Descriptions
L2_STATUS_MSR Register Map
L2_STATUS_MSR Bit Descriptions
L2_INDEX_MSR Register Map
L2_INDEX_MSR Bit Descriptions
L2_DATA_MSR Register Map
L2_DATA_MSR Bit Descriptions
L2_TAG_MSR Register Map
L2_TAG_MSR Bit Descriptions
L2_TAG_I_MSR Register Map
L2_BIST_MSR Register Map
L2_BIST_MSR Bit Descriptions
L2_BIST_MSR Bit Descriptions (Continued)
L2_TRTMNT_CTL_MSR Register Map
L2_TRTMNT_CTL_MSR Bit Descriptions
PMODE_MSR Register Map
PMODE_MSR Bit Descriptions
BXDR1_BXDR0_MSR Register Map
BXDR1_BXDR0_MSR Bit Descriptions
BXDR3_BXDR2_MSR Register Map
BXDR3_BXDR2_MSR Bit Descriptions
BXDR6_BXDR7_MSR Register Map
BXDR6_BXDR7_MSR Bit Descriptions
BXDR6_BXDR7_MSR Bit Descriptions (Continued)
BDRx_MSR Register Map
BDRx_MSR Bit Descriptions
BDR6_MSR Register Map
BDR6_MSR Bit Descriptions
BDR7_MSR Register Map
BDR7_MSR Bit Descriptions
MSS_ARRAY_CTL_EN_MSR Register Map
MSS_ARRAY_CTL_EN_MSR Bit Descriptions
MSS_ARRAY_CTL0_MSR Register Map
MSS_ARRAY_CTL0_MSR Bit Descriptions
MSS_ARRAY_CTL1_MSR Register Map
MSS_ARRAY_CTL1_MSR Bit Descriptions
MSS_ARRAY_CTL2_MSR Register Map
MSS_ARRAY_CTL2_MSR Bit Descriptions
FP_MODE_MSR Register Map
FP_MODE_MSR Bit Descriptions
FPU_CW_MSR Register Map
FPU_CW_MSR Bit Descriptions
FPU_SW_MSR Register Map
FPU_SW_MSR Bit Descriptions
FPU_TW_MSR Register Map
FPU_TW_MSR Bit Descriptions
FPU_BUSY_MSR Register Map
FPU_BUSY_MSR Bit Descriptions
FPU_MAP_MSR Register Map
FPU_MAP_MSR Bit Descriptions
FPU_MRx_MSR Bit Descriptions
FPU_ERx_MSR Register Map
FPU_ERx_MSR Bit Descriptions
Page
CPUIDx_MSR Register Map
CPUIDx_MSR Bit Descriptions
6.0Integrated Functions
SDCLKs
Figure 6-1. Integrated Functions Block Diagram
6.1 GeodeLink Memory Controller
Figure 6-2. GLMC Block Diagram
Page
Figure 6-5. LOI Addressing Example
Figure 6-6. LOI Example
CA are the CAS addresses on MA[7:0]
MB[1]
Internal Physical Address
Table 6-1. LOI - 2 DIMMs, Same Size, 1 DIMM Bank
Table 6-2. LOI - 2 DIMMs, Same Size, 2 DIMM Banks
Table 6-3. Non-Auto LOI - 1 or 2 DIMMs, Different Sizes, 1 DIMM Bank
Table 6-4. Non-Auto LOI - 1 or 2 DIMMs, Different Sizes, 2 DIMM Banks
Figure 6-7. Request Pipeline
Figure 6-8. DDR Reads
Figure 6-9. DDR Writes
6.1.2 Power Control
6.2 GeodeLink Memory Controller Register Descriptions
Table 6-5. Standard GeodeLink Device MSRs Summary
Table 6-6. GLMC Specific MSR Summary
6.2.1 Standard GeodeLink Device (GLD) MSRs
Table 6-6. GLMC Specific MSR Summary
GLD_MSR_CAP Register
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6.2.2 GLMC Specific MSRs
MC_CF_BANK01 Register Map
MC_CF_BANK01 Bit Descriptions
MC_CF_BANK23 Register Map
MC_CF_BANK23 Bit Descriptions
MC_CF_BANK45 Register Map
MC_CF_BANK45 Bit Descriptions
MC_CF_BANK67 Register Map
MC_CF_BANK67 Bit Descriptions
MC_CF_BANK89 Register Map
MC_CF_BANK89 Bit Descriptions
MC_CF_BANKAB Register Map
MC_CF_BANKAB Bit Descriptions
MC_CF_BANKCD Register Map
MC_CF_BANKCD Bit Descriptions
MC_CF_BANKEF Register Map
MC_CF_BANKEF Bit Descriptions
MC_CF07_DATA Register Map
MC_CF07_DATA Bit Descriptions
Page
MC_CF07_DATA Bit Descriptions (Continued)
MC_CF8F_DATA Register Map
MC_CF8F_DATA Bit Descriptions
MC_CF8F_DATA Bit Descriptions (Continued)
MC_CF1017_DATA Register Map
MC_CF1017_DATA Bit Descriptions
MC_CFPERF_CNT1 Register Map
MC_CFPERF_CNT1 Bit Descriptions
MC_PERFCNT2 Register Map
MC_PERFCNT2 Bit Descriptions
MC_CFCLK_DBUG Register Map
MC_CFCLK_DBUG Bit Descriptions
MC_CFPG_OPEN Register Map
MC_CFPG_OPEN Bit Descriptions
MC_CF_PMCTR Register Map
MC_CF_PMCTR Bit Descriptions
6.3 Graphics Processor
Figure 6-10. Graphics Processor Block Diagram
Table 6-7. Graphics Processor Feature Comparison
6.3.1 Command Buffer
Table 6-8. BLT Command Buffer Structure
Table 6-9. Vector Command Buffer Structure
Table 6-10. LUT (Lookup Table) Load Command Buffer Structure
Table 6-11. Data Only Command Buffer Structure
6.3.2 Channel 3
Table 6-12. Bit Descriptions
Page
Table 6-13. Pixel Ordering for 4-Bit Pixels
Figure 6-11. 14-Bit Repeated Pattern
Table 6-14. Example Vector Pattern
Table 6-15. Example Vector Length
6.3.3 BLT Operation
6.3.4 Vector Operation
6.3.5 Pipelined Operation
6.3.6 Pattern Generation
Table 6-16. Example of Monochrome Pattern
Table 6-17. Example of 8-Bit Color Pattern (3:3:2 Format)
Table 6-18. Example of 16-Bit Color Pattern (5:6:5 Format)
6.3.7 8x8 Color Patterns
6.3.8 Source Data
Table 6-19. 32-bpp 8:8:8:8 Color Data Format
Table 6-20. 16-bpp Color Data Format
Table 6-21. 8-bpp 3:3:2 Color Data Format
Table 6-23. Example of Byte-Packed Monochrome Source Data
Table 6-24. Example of Unpacked Monochrome Source Data
6.3.9 Destination Data
6.3.10 Raster Operations (ROP)
Table 6-25. GP_RASTER_MODE Bit Patterns
Table 6-26. Common Raster Operations
6.3.11 Image Compositing Using Alpha
Table 6-27. Alpha Blending Modes
Table 6-27. Alpha Blending Modes (Continued)
6.4 Graphics Processor Register Definitions
Table 6-28. Standard GeodeLink Device MSRs Summary
Table 6-29. Graphics Processor Configuration Register Summary
6.4.1 Standard GeodeLink Device (GLD) MSRs
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6.4.2 Graphics Processor Configuration Registers
GP_DST_OFFSET Register Map
GP_DST_OFFSET Bit Descriptions
GP_SRC_OFFSET Register Map
GP_SRC_OFFSET Bit Descriptions
GP_SRC_OFFSET Bit Descriptions (Continued)
GP_VEC_ERR Register Map
GP_VEC_ERR Bit Description
GP_STRIDE Register Map
GP_STRIDE Bit Descriptions
GP_WID_HEIGHT Register Map
GP_WID_HEIGHT Bit Descriptions
GP_VEC_LEN Register Map
GP_VEC_LEN Bit Descriptions
GP_SRC_COLOR_FG Register Map
GP_SRC_COLOR_FG Bit Descriptions
GP_SRC_COLOR_BG Register Map
GP_SRC_COLOR_BG Bit Descriptions
Table 6-30. PAT_COLOR Usage for Color Patterns
GP_PAT_COLOR_x Register Map
GP_PAT_COLOR_x Bit Descriptions
Table 6-31. PAT_DATA Usage for Color Patterns
GP_PAT_DATA_x Register Map
GP_PAT_DATA_x Bit Descriptions
GP_RASTER_MODE Register Map
GP_RASTER_MODE Bit Descriptions
GP_RASTER_MODE Bit Descriptions (Continued)
GP_VECTOR_MODE Register Map
GP_VECTOR_MODE Bit Descriptions
GP_BLT_MODE Register Map
GP_BLT_MODE Bit Descriptions
GP_BLT_STATUS Register Map
GP_ BLT_S TATUS Bit Des cri pti ons
GP_HST_SRC Register Map
GP_HST_SRC Bit Descriptions
GP_BASE_OFFSET Register Map
GP_BASE_OFFSET Bit Descriptions
GP_CMD_TOP Register Map
GP_CMD_TOP Bit Descriptions
GP_CMD_BOT Register Map
GP_CMD_BOT Bit Descriptions
GP_CMD_READ Register Map
GP_CMD_READ Bit Descriptions
GP_CMD_WRITE Register Map
GP_CMD_WRITE Bit Descriptions
GP_CH3_OFFSET Register Map
GP_CH3_OFFSET Bit Descriptions
GP_CH3_MODE_STR Register Map
GP_CH3_MODE_STR Bit Descriptions
GP_CH3_MODE_STR Bit Descriptions (Continued)
GP_CH3_WIDHI Register Map
GP_CH3_WIDHI Bit Descriptions
Page
GP_INT_CNTRL Register Map
GP_INT_CNTRL Bit Descriptions
6.5 Display Controller
VGA Block
Figure 6-12. Display Controller High-Level Block Diagram
Graphical User Interface Block
Figure 6-13. GUI Block Diagram
Figure 6-14. VGA Block Diagram
6.5.1 GUI Functional Overview
Table 6-32. Display Modes
Table 6-32. Display Modes (Continued)
Table 6-33. Cursor Display Encodings
Table 6-34. Icon Display Encodings
Table 6-35. Cursor/Color Key/Alpha Interaction
Page
Table 6-36. Video Bandwidth
Table 6-37. YUV 4:2:0 Video Data Ordering
Table 6-38. YUV 4:2:2 Video Data Ordering
6.5.4 VGA Block Functional Overview
Figure 6-15. VGA Frame Buffer Organization
Table 6-39. VGA Text Modes
Table 6-40. Text Mode Attribute Byte Format
Table 6-41. VGA Graphics Modes
Figure 6-16. Graphics Controller High-level Diagram
Figure 6-17. Write Mode Data Flow
Figure 6-18. Read Mode Data Flow
Figure 6-19. Color Compare Operation
6.5.6 Graphics Scaler/Filter
Figure 6-20. Graphics Filter Block Diagram
Figure 6-20. Graphics Filter Block Diagram (Continued)
Figure 6-21. Flicker Filter and Line Buffer Path
Page
Table 6-42. Programming Image Sizes
6.5.10 Interlaced Timing Examples
Figure 6-22. Interlaced Timing Settings
Table 6-43. Vertical Timing in Number of Lines
Table 6-44. Timing Register Settings for Interlaced Modes
6.6 Display Controller Register Descriptions
Table 6-45. Standard GeodeLink Device MSRs Summary
Table 6-46. DC Specific MSRs Summary
Table 6-47. DC Configuration Control Register Summary
Page
Table 6-47. DC Configuration Control Register Summary (Continued)
Table 6-48. VGA Block Configuration Register Summary
Table 6-49. VGA Block Standard Register Summary
Table 6-50. VGA Block Extended Register Summary
6.6.1 Standard GeodeLink Device (GLD) Registers (MSRs)
Page
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GLD_MSR_SMI Bit Descriptions (Continued)
Page
Page
6.6.2 Display Controller Specific MSRs
SPARE_MSR Register Map
SPARE_MSR Bit Descriptions
DC_RAM_CTL_MSR Register Map
DC_RAM_CTL_MSR Bit Descriptions
Page
DC_UNLOCK Bit Descriptions
DC_GENERAL_CFG Register Map
DC_GENERAL_CFG Bit Descriptions
Page
DC_GENERAL_CFG Bit Descriptions (Continued)
DC_DISPLAY_CFG Register Map
DC_DISPLAY_CFG Bit Descriptions
DC_DISPLAY_CFG Bit Descriptions (Continued)
DC_ARB_CFG Register Map
DC_ARB_CFG Bit Descriptions
DC_ARB_CFG Bit Descriptions (Continued)
6.6.4 Memory Organization Registers
DC_FB_ST_OFFSET
DC_FB_ST_OFFSET Bit Descriptions
DC_CB_ST_OFFSET Register Map
DC_CB_ST_OFFSET Bit Descriptions
DC_CURS_ST_OFFSET Register Map
DC_CURS_ST_OFFSET Bit Descriptions
DC_VID_Y_ST_OFFSET Register Map
DC_VID_Y_ST_OFFSET Bit Descriptions
DC_VID_U_ST_OFFSET Register Map
DC_VID_U_ST_OFFSET Bit Descriptions
DC_VID_V_ST_OFFSET Register Map
DC_VID_V_ST_OFFSET Bit Descriptions
DC_DV_TOP Register Map
DC_DV_TOP Bit Descriptions
DC_LINE_SIZE Register Map
DC_LINE_SIZE Bit Descriptions
DC_GFX_PITCH Register Map
DC_GFX_PITCH Bit Descriptions
DC_VID_YUV_PITCH Register Map
DC_VID_YUV_PITCH Bit Descriptions
6.6.5 Timing Registers
DC_H_ACTIVE_TIMING Register Map
DC_H_ACTIVE_TIMING Bit Descriptions
DC_H_BLANK_TIMING Register Map
DC_H_BLANK_TIMING Bit Descriptions
DC_H_SYNC_TIMING Register Map
DC_H_SYNC_TIMING Bit Descriptions
DC_V_ACTIVE_TIMING Register Map
DC_V_ACTIVE_TIMING Bit Descriptions
DC_V_BLANK_TIMING Register Map
DC_V_BLANK_TIMING Bit Descriptions
DC_V_SYNC_TIMING Register Map
DC_V_SYNC_TIMING Bit Descriptions
6.6.6 Cursor Position and Line Count/Status Registers
DC_FB_ACTIVE Register Map
DC_FB_ACTIVE Bit Descriptions
DC_CURSOR_X Register Map
DC_CURSOR_X Bit Descriptions
DC_CURSOR_Y Register Map
DC_CURSOR_Y Bit Descriptions
DC_LINE_CNT/STATUS Register Map
DC_LINE_CNT/STATUS Bit Descriptions
6.6.7 Palette Access FIFO Diagnostic Registers
DC_PAL_ADDRESS Register Map
DC_PAL_ADDRESS Bit Descriptions
DC_PAL_DATA Register Map
DC_PAL_DATA Bit Descriptions
DC_DFIFO_DIAG Register Map
DC_DFIFO_DIAG Bit Descriptions
DC_CFIFO_DIAG Register Map
DC_CFIFO_DIAG Bit Descriptions
6.6.8 Video Downscaling
DC_VID_DS_DELTA Register Map
DC_VID_DS_DELTA Bit Descriptions
6.6.9 GLIU Control Registers
DC_GLIU0_MEM_OFFSET Register Map
DC_GLIU0_MEM_OFFSET Bit Descriptions
DC_DV_CTL Register Map
DV_CTL Bit Descriptions
DV_CTL Bit Descriptions (Continued)
DC_DV_ACCESS Register Map
DC_DV_ACCESS Bit Descriptions
6.6.10 Graphics Scaling Control Registers
DC_GFX_SCALE Register Map
DC_GFX_SCALE Bit Descriptions
DC_IRQ_FILT_CTL Register Map
DC_IRQ_FILT_CTL Bit Descriptions
DC_IRQ_FILT_CTL Bit Descriptions (Continued)
DC_FILT_COEFF1 Register Map
DC_ FILT_COEFF1 Bit Descriptions
6.6.11 VBI Control Registers
DC_FILT_COEFF2 Register Map
DC_FILT_COEFF2 Bit Descriptions
DC_VBI_EVEN_CTL Register Map
DC_VBI_EVEN_CTL Bit Descriptions
DC_VBI_EVEN_CTL Bit Descriptions (Continued)
DC_VBI_ODD_CTL Register Map
DC_VBI_ODD_CTL Bit Descriptions
DC_VBI_HOR Register Map
DC_VBI_HOR Bit Descriptions
DC_VBI_LN_ODD Register Map
DC_VBI_LN_ODD Bit Descriptions
DC_VBI_LN_EVEN Register Map
DC_VBI_LN_EVEN Bit Descriptions
6.6.12 Color Key Control Registers
DC_VBI_PITCH Register Map
DC_VBI_PITCH Bit Descriptions
DC_CLR_KEY Register Map
DC_CLR_KEY Bit Descriptions
DC_CLR_KEY_MASK Register Map
DC_CLR_KEY_MASK Bit Descriptions
DC_CLR_KEY_X Register Map
DC_CLR_KEY_X Bit Descriptions
DC_CLR_KEY_Y Register Map
DC_CLR_KEY_Y Bit Descriptions
DC_IRQ Register Map
DC_IRQ Bit Descriptions
6.6.13 Interrupt and GenLock Registers
DC_GENLK_CTL Register Map
DC_GENLK_CTL Bit Descriptions
6.6.14 Even Field Video Address Registers
DC_GENLK_CTL Bit Descriptions (Continued)
DC_VID_EVEN_Y_ST_OFFSET Register Map
DC_VID_EVEN_Y_ST_OFFSET Bit Descriptions
DC_VID_EVEN_U_ST_OFFSET Register Map
DC_VID_EVEN_U_ST_OFFSET Bit Descriptions
DC_VID_EVEN_V_ST_OFFSET Register Map
DC_VID_EVEN_V_ST_OFFSET Bit Descriptions
6.6.15 Even Field Vertical Timing Registers
DC_V_ACTIVE_EVEN_TIMING Register Map
DC_V_ACTIVE_EVEN_TIMING Bit Descriptions
DC_V_BLANK_EVEN_TIMING Register Map
DC_V_BLANK_EVEN_TIMING Bit Descriptions
DC_V_SYNC_EVEN_TIMING Register Map
DC_V_SYNC_EVEN_TIMING Bit Descriptions
6.6.16 VGA Block Configuration Registers
VGA_CONFIG Register Map
VGA_CONFIG Bit Descriptions
VGA_STATUS Register Map
VGA_STATUS Bit Descriptions
6.6.17 VGA Block Standard Registers
VGA_STATUS Bit Descriptions (Continued)
VGA Miscellaneous Output Register Bit Descriptions
VGA Input Status Register 0 Bit Descriptions
VGA Input Status Register 1 Bit Descriptions
VGA Feature Control Register Bit Descriptions
6.6.18 VGA Sequencer Registers
Table 6-51. VGA Sequencer Registers Summary
VGA Sequencer Index Register Bit Descriptions
VGA Sequencer Data Register Bit Descriptions
VGA Reset Register Bit Descriptions
VGA Clocking Mode Register Bit Descriptions
VGA Map Mask Register Bit Descriptions
VGA Character Map Select Register Bit Descriptions
Table 6-52. Font Table
VGA Memory Mode Register Bit Descriptions
6.6.19 VGA CRT Controller Registers
Table 6-53. CRTC Register Settings
Table 6-54. CRTC Registers Summary
CRTC Index Register Bit Descriptions
CRTC Data Register Bit Descriptions
Horizontal Total Register Bit Descriptions
Horizontal Display Enable End Register Bit Descriptions
Horizontal Blank Start Register Bit Descriptions
Horizontal Blank End Register Bit Descriptions
Horizontal Sync Start Register Bit Descriptions
Horizontal Sync End Register Bit Descriptions
Vertical Total Register Bit Descriptions
Overflow Register Bit Descriptions
Preset Row Scan Register Bit Descriptions
Maximum Scan Line Register Bit Descriptions
Cursor Start Register Bit Descriptions
Cursor End Register Bit Descriptions
Start Address High Register Bit Descriptions
Start Address Low Register Bit Descriptions
Cursor Location High Register Bit Descriptions
Cursor Location Low Register Bit Descriptions
Vertical Sync Start Register Bit Descriptions
Vertical Sync End Register Bit Descriptions
Vertical Display Enable End Register Bit Descriptions
Offset Register Bit Descriptions
Underline Location Register Bit Descriptions
Vertical Blank Start Register Bit Descriptions
Vertical Blank End Register Bit Descriptions
CRTC Mode Control Register Bit Descriptions
Table 6-55. CRTC Memory Addressing Modes
CRTC Mode Control Register Bit Descriptions (Continued)
Line Compare Register Bit Descriptions
CPU Data Latch State Register Bit Descriptions
Attribute Index/Data FF State Register Bit Descriptions
6.6.20 VGA Graphics Controller Registers
Attribute Index State Register Bit Descriptions
Table 6-56. Graphics Controller Registers Summary
VGA Graphics Controller Index Register Bit Descriptions
VGA Graphics Controller Data Register Bit Descriptions
VGA Set/Reset Register Bits Bit Descriptions
VGA Enable Set/Reset Register Bit Descriptions
VGA Color Compare Register Bit Descriptions
VGA Data Rotate Bit Descriptions Bit Descriptions
VGA Read Map Select Register Bit Descriptions
VGA Graphics Mode Register Bit Descriptions
VGA Miscellaneous Register Bit Descriptions
VGA Graphics Mode Register Bit Descriptions
6.6.21 Attribute Controller Registers
VGA Color Dont Care Register Bit Descriptions
VGA Bit Mask Register Bit Descriptions
Table 6-57. Attribute Controller Registers Summary
Attribute Controller Index Register Bit Descriptions
EGA Palette Register Bit Descriptions
Attribute Mode Control Register Bit Descriptions
Overscan Color Register Bit Descriptions
Color Plane Enable Register Bit Descriptions
Horizontal Pel Panning Register Bit Descriptions
6.6.22 Video DAC Registers
Color Select Register Bit Descriptions
Table 6-58. Video DAC Registers Summary
Video DAC Palette Address Register Bit Descriptions
Video DAC State Register Bit Descriptions
Video DAC Palette Data Register Bit Descriptions
6.6.23 VGA Block Extended Registers
Video DAC Palette Mask Register Bit Descriptions
Table 6-59. Extended Registers Summary
ExtendedRegisterLock Register Bit Descriptions
ExtendedModeControl Register Bit Descriptions
ExtendedStartAddress Register Bit Descriptions
WriteMemoryAperture Register Bit Descriptions
ReadMemoryAperture Register Bit Descriptions
BlinkCounterCtl Register Bit Descriptions
BlinkCounter Register Bit Descriptions
VGALatchSavRes Register Bit Descriptions
DACIFSavRes Register Bit Descriptions
6.7 Video Processor
6.7.1 Architecture Overview
Figure 6-23. Video Processor Block Diagram
Video Processor
Flat Panel Display Controller
Video Processor Module
Figure 6-24. Video Processor Block Diagram
Page
Figure 6-25. Downscaler Block Diagram
6.7.3 X and Y Upscaler
6.7.4 Color Space Converter
Figure 6-26. Linear Interpolation Calculation
6.7.5 Video Overlay
Figure 6-27. Mixer Block Diagram
Figure 6-28. Color Key and Alpha-Blending Logic
Use video value for this pixel
Table 6-60. Truth Table for Alpha-Blending
6.7.6 Video Output Port
Figure 6-29. VOP Internal Block Diagram
Figure 6-30. 525-Line NTSC Video Window
Figure 6-31. HBLANK and VBLANK for Lines 20-262, 283-524
Figure 6-32. HBLANK and VBLANK for Lines 263, 525
Figure 6-33. HBLANK and VBLANK for Lines 1-18, 264-281
Figure 6-34. HBLANK and VBLANK for Lines 19, 282
Table 6-61. VOP Mode
Table 6-62. SAV/EAV Sequence
Table 6-63. Protection Bit Values
Figure 6-35. BT.656 8/16 Bit Line Data
Table 6-64. SAV VIP Flags
Table 6-65. VOP Clock Rate
6.7.7 Flat Panel Display Controller
Figure 6-36. Flat Panel Display Controller Block Diagram
Table 6-66. Panel Output Signal Mapping
Table 6-66. Panel Output Signal Mapping (Continued)
Figure 6-37. Dithered 8x8 Pixel Pattern
Figure 6-38. N-Bit Dithering Pattern Schemes
4-Bit Scheme 3-Bit Scheme
2-Bit Scheme 1-Bit Scheme
Table 6-67. Register Settings for Dither Enable/ Disable Feature
6.7.8 VP Resolution Table
6.7.9 Display RGB Modes
Table 6-68. Display RGB Modes
6.8 Video Processor Register Descriptions
Table 6-69. Standard GeodeLink Device MSRs Summary
Table 6-70. Video Processor Module Specific MSRs Summary
Table 6-71. Video Processor Module Configuration Control Registers Summary
Page
Table 6-71. Video Processor Module Configuration Control Registers Summary (Continued)
6.8.1 Standard GeodeLink Device MSRs
GLD_MSR_CONFIG Bit Descriptions (Continued)
Page
Page
6.8.2 Video Processor Module Specific MSRs
MSR_DIAG_VP Register Map
MSR_DIAG_VP Bit Descriptions
MSR_PADSEL Register Map
MSR_PADSEL Bit Descriptions
6.8.3 Video Processor Module Control/Configuration Registers
VCFG Register Map
VCFG Bit Descriptions
VCFG Bit Descriptions (Continued)
DCFG Register Map
DCFG Bit Descriptions
DCFG Bit Descriptions (Continued)
VX Register Map
VX Bit Descriptions
VY Register Map
VY Bit Descriptions
SCL Register Map
SCL Bit Descriptions
VCK Register Map
VCK Bit Descriptions
VCK Bit Descriptions (Continued)
VCM Register Map
VCM Bit Descriptions
PAR Register Map
PAR Bit Descriptions
PDR Register Map
PDR Bit Descriptions
SLR Register Map
SLR Bit Descriptions
MISC Register Map
MISC Bit Descriptions
VYS Register Map
VYS Bit Descriptions
VXS Register Map
VXS Bit Descriptions
VDC Register Map
VDC Bit Descriptions
CRC Register Map
CRC Bit Descriptions
CRC32 Register Map
CRC32 Bit Descriptions
VDE Register Map
VDE Bit Descriptions
Page
VDE Bit Descriptions (Continued)
CCK Register Map
CCK Bit Descriptions
CCM Register Map
CCM Bit Descriptions
CC1 Register Map
CC1 Bit Descriptions
CC2 Register Map
CC2 Bit Descriptions
A1X Register Map
A1X Bit Descriptions
A1Y Register Map
A1Y Bit Descriptions
A1C Register Map
A1C Bit Descriptions
A1T Register Map
A1T Bit Descriptions
A2X Register Map
A2X Bit Descriptions
A2Y Register Map
A2Y Bit Descriptions
A2C Register Map
A2C Bit Descriptions
A2T Register Map
A2T Bit Descriptions
A2T Bit Descriptions (Continued)
A3X Register Map
A3X Bit Descriptions
A3Y Register Map
A3Y Bit Descriptions
A3C Register Map
A3C Bit Descriptions
A3T Register Map
A3T Bit Descriptions
A3T Bit Descriptions (Continued)
VRR Register Map
VRR Bit Descriptions
AWT Register Map
AWT Bit Descriptions
VTM Register Map
VTM Bit Descriptions
VYE Register Map
VYE Bit Descriptions
A1YE Register Map
A1YE Bit Descriptions
A2YE Register Map
A2YE Bit Descriptions
A3YE Register Map
A3YE Bit Descriptions
VCR Register Map
VCR Bit Descriptions
PT1 Register Map
PT1 Bit Descriptions
PT1 Bit Descriptions (Continued)
PT2 Register Map
PT2 Bit Descriptions
PT2 Bit Descriptions (Continued)
PM Register Map
PM Bit Descriptions
PM Bit Descriptions (Continued)
DFC Register Map
DFC Bit Descriptions
DFC Bit Descriptions (Continued)
DCA Register Map
DCA Bit Descriptions
DMD Register Map
DMD Bit Descriptions
CRC Register Map
CRC Bit Descriptions
CRC32 Register Map
CRC32 Bit Descriptions
Page
Page
6.9 Video Input Port
6.9.1 Features
Table 6-72.
6.9.2 VIP Block Descriptions
Figure 6-39. VIP Block Diagram
Page
6.9.3 Functional Description
6.9.4 VIP Operation Modes
6.9.5 Mode 1a,b,c - VIP Input Data (simplified BT.656)
Table 6-73. SAV/EAV Sequence
Figure 6-40. BT.656, 8/16-Bit Line Data
Figure 6-41. 525 line , 60 Hz Digital Vertical Timing
Figure 6-42. Ancillary Data Packets
6.9.6 Message Passing Mode
6.9.7 Data Streaming Mode
Figure 6-43. Message Passing Data Packet
Figure 6-44. Data Streaming Data Packet
6.9.8 BT.601 Mode
Figure 6-45. BT.601 Mode Default Field Detection
Figure 6-46. BT.601 Mode Programmable Field Detection
Figure 6-47. BT.601 Mode Horizontal Timing
Figure 6-48. BT.601 Mode Vertical Timing 6.9.9 YUV 4:2:2 to YUV 4:2:0 Translation
Figure 6-49. YUV 4:2:2 to YUV 4:2:0 Translation
6.9.10 Software Model
Table 6-74. VIP Data Types / Memory Registers
Figure 6-50. Dual Buffer for Message Passing and Data Streaming Modes
Figure 6-51. Example VIP YUV 4:2:2 SAV/EAV Packets Stored in System Memory in a Linear Buffer
Figure 6-52. Example VIP YUV 4:2:0 Planar Buffer
Figure 6-53. Example VIP 8/16- and 10-bit Ancillary Packets Stored in System Memory
6.9.11 Bob and Weave
6.9.12 VIP Interrupts
6.9.13 VIP Input Video Status
6.10 Video Input Port Register Descriptions
Table 6-75. Standard GeodeLink Device MSRs Summary
Table 6-76. VIP Configuration/Control Registers Summary
6.10.1 Standard GeodeLink Device (GLD) MSRs
GLD_MSR_CAP Bit Descriptions
Page
Page
Page
6.10.2 VIP Control/Configuration Registers
VIP_CTL_REG1 Register Map
VIP_CTL_REG1 Bit Descriptions
Page
VIP_CTL_REG1 Bit Descriptions (Continued)
VIP_CTL_REG2 Register Map
VIP_CTL_REG2 Bit Descriptions
VIP_CTL_REG2 Bit Descriptions (Continued)
VIP_STATUS Register Map
VIP_STATUS Bit Descriptions
VIP_STATUS Bit Descriptions (Continued)
VIP_INT Register Map
VIP_INT Bit Descriptions
VIP_CUR_TAR Register Map
VIP_CUR_TAR Register Bit Descriptions
VIP_MAX_ADDR Register Map
VIP_MAX_ADDR Bit Descriptions
VIP_TASK_A_VID_EVEN_BASE Register Map
VIP_TASK_A_VID_EVEN_BASE Bit Descriptions
VIP_TASK_A_VID_ODD_BASE Register Map
VIP_TASK_A_VID_ODD_BASE Bit Descriptions
VIP_TASK_A_VBI_EVEN_BASE Register Map
VIP_TASK_A_VBI_EVEN_BASE Bit Descriptions
VIP_TASK_A_VBI_ODD_BASE Register Map
VIP_TASK_A_VBI_ODD_BASE Bit Description
VIP_TASK_A_VID_PITCH Register Map
VIP_TASK_A_VID_PITCH Bit Descriptions
VIP_CONTRL_REG3 Register Map
VIP_CONTRL_REG3 Bit Descriptions
VIP_CONTRL_REG3 Bit Descriptions (Continued)
VIP_TASK_A_V_OFFSET Register Map
VIP_TASK_A_V_OFFSET Bit Descriptions
VIP_TASK_A_U_OFFSET Register Map
VIP_TASK_A_U_OFFSET Bit Descriptions
VIP_TASK_B_VID_EVEN_BASE_HORIZ_END Register Map
VIP_TASK_B_VID_EVEN_BASE_HORIZ_END Bit Descriptions
VIP_TASK_B_VID_ODD_BASE_HORIZ_START Register Map
VIP_TASK_B_VID_ODD_BASE_HORIZ_START Bit Descriptions
VIP_TASK_B_VBI_EVEN_BASE_VBI_END Register Map
VIP_TASK_B_VBI_EVEN_BASE_VBI_END Bit Descriptions
VIP_TASK_B_VBI_EVEN_BASE_VBI_END Bit Descriptions (Continued)
VIP_TASK_B_VBI_ODD_BASE_VBI_START Register Map
VIP_TASK_B_VBI_ODD_BASE_VBI_START BIt Descriptions
VIP_TASK_B_DATA_PITCH_VERT_START_EVEN Register Map
VIP_TASK_B_DATA_PITCH_VERT_START_EVEN BIT Descriptions
VIP_TASK_B_DATA_PITCH_VERT_START_EVEN BIT Descriptions (Continued)
VIP_TASK_B_V_OFFSET Register Map
VIP_TAS_B_V_OFFSET Bit Descriptions
VIP_TASK_B_U_OFFSET Register Map
VIP_TASK_B_U_OFFSET Bit Descriptions
VIP_ANC_MSG_1_BASE Register Map
VIP_ANC_MSG_1_BASE Bit Descriptions
VIP_ANC_MSG_2_BASE Register Map
VIP_ANC_MSG_2_BASE Bit Descriptions
VIP_ANC_MSG_SIZE Register Map
VIP_ANC_MSG_SIZE Bit Descriptions
VIP_PAGE_OFFSET Register Map
VIP_PAGE_OFFSET Bit Descriptions
VIP_VERT_START_STOP Register Map
VIP_VERT_START_STOP Bit Description
VIP_FIFO_R_W_ADDR Register Map
VIP_FIFO_R_W_ADDR Bit Descriptions
VIP_FIFO_DATA Register Map
VIP_FIFO_DATA Bit Descriptions
VIP_SYNC_ERR_COUNT Register Map
VIP_SYNC_ERR_COUNT Bit Descriptions
VIP_TASK_A_U_EVEN_OFFSET Register Map
VIP_TASK_A_U_EVEN_OFFSET Bit Descriptions
VIP_TASK_A_V_EVEN_OFFSET Register Map
VIP_TASK_A_V_EVEN_OFFSET Bit Descriptions
6.11 Security Block
6.11.1 Security Block Features
Figure 6-54. Security Block Diagram
6.11.2 Functional Description
Table 6-77. EEPROM Address Map
6.12 Security Block Register Descriptions
Table 6-78. Standard GeodeLink Device MSRs Summary
Table 6-79. Security Block Specific MSRs
Table 6-80. Security Block Configuration/Control Registers Summary
Table 6-80. Security Block Configuration/Control Registers Summary (Continued)
6.12.1 Standard GeodeLink (GLD) Device MSRs
Page
Page
Page
6.12.2 Security Block Specific MSRs
GLD_MSR_CTRL Register Map
GLD_MSR_CTRL Bit Descriptions
6.12.3 Security Block Configuration/Control Registers
GLD_MSR_CTRL Bit Descriptions (Continued)
SB_CTL_A Register Map
SB_CTL_A Register Bit Descriptions
SB_CTL_A Register Bit Descriptions (Continued)
SB_CTL_B Register Map
SB_CTL_B Register Bit Descriptions
SB_AES_INT Register Map
SB_AES_INT Register Bit Descriptions
SB_SOURCE_A Register Map
SB_SOURCE_A Register Bit Descriptions
SB_DEST_A Register Map
SB_DEST_A Register Bit Descriptions
SB_LENGTH_A Register Map
SB_LENGTH_A Register Bit Descriptions
SB_SOURCE_B Register Map
SB_SOURCE_B Register Bit Descriptions
SB_DEST_B Register Map
SB_DEST_B Register Bit Descriptions
SB_LENGTH_B Register Map
SB_LENGTH_B Register Bit Descriptions
SB_WKEY_1 Register Map
SB_WKEY_1 Bit Descriptions
SB_WKEY_2 Register Map
SB_WKEY_2 Bit Descriptions
SB_WKEY_3 Register Map
SB_WKEY_3 Bit Descriptions
SB_CBC_IV_0 Register Map
SB_CBC_IV_0 Bit Descriptions
SB_CBC_IV_1 Register Map
SB_CBC_IV_1 Bit Descriptions
SB_CBC_IV_2 Register Map
SB_CBC_IV_2 Bit Descriptions
SB_CBC_IV_3 Register Map
SB_RANDOM_NUM Register Map
SB Random Number Bit Descriptions
SB_RANDOM_NUM_STATUS Register Map
SB_RANDOM_NUM_STATUS Bit Descriptions
SB_EEPROM_COMM Register Map
SB_EEPROM_COMM Bit Descriptions
SB_EEPROM_ADDR Register Map
SB_EEPROM_ADDR Bit Descriptions
SB_EEPROM_DATA Register Map
SB_EEPROM_DATA Bit Descriptions
SB_EEPROM_SEC_STATE Register Map
SB_EEPROM_SEC_STATE Bit Descriptions
6.13 GeodeLink Control Processor
6.13.1 TAP Controller
Figure 6-55. GLCP Block Diagram
Table 6-81. TAP Control Instructions (25-Bit IR)
Table 6-82. TAP Instruction Bits
6.13.2 Reset Logic
6.13.3 Clock Control
Figure 6-56. Processor Clock Generation 6.13.4 Companion Device Interface
Figure 6-57. GIO Interface Block Diagram
Table 6-83. GIO_PCI Outputs
Table 6-84. CIS Signaling Protocol
6.14 GeodeLink Control Processor Register Descriptions
Table 6-85. Standard GeodeLink Device MSRs Summary
Table 6-86. GLCP Specific MSRs Summary
Table 6-86. GLCP Specific MSRs Summary (Continued)
6.14.1 Standard GeodeLink Device MSRs
GLD_MSR_CAP Bit Descriptions
GLD_MSR_CONFIG Bit Descriptions
Page
Page
Page
6.14.2 GLCP Specific MSRs - GLCP Control MSRs
GLCP_CLK_DIS_DELAY Register Map
GLCP_CLK_DIS_DELAY Bit Descriptions
GLCP_PMCLKDISABLE Register Map
GLCP_PMCLKDISABLE Bit Descriptions
GLCP_PMCLKDISABLE Bit Descriptions (Continued)
GLCP_GLB_PM Register Map
GLCP_GLB_PM Bit Descriptions
GLCP_PROCSTAT Register Map
GLCP_PROCSTAT Bit Descriptions
GLCP_DOWSER Register Map
GLCP_DOWSER Bit Descriptions
GLCP_DELAY_CONTROLS Register Map
GLCP_DELAY_CONTROLS Bit Definition
GLCP_DELAY_CONTROLS Bit Definition (Continued)
GLCP_CLKOFF Register Map
GLCP_CLKOFF Bit Descriptions
GLCP_CLKOFF Bit Descriptions (Continued)
GLCP_CLKACTIVE Register Map
6.14.2.11GLCP Clock Mask for Debug Clock Stop Action (GLCP_CLKDISABLE)
See "GLCP_CLKOFF Bit Descriptions" on page 551 for bit descriptions.
MSR Address 4C000012h Type R/W Reset Value 00000000_00000000h
GLCP_CLKDISABLE Register Map
MSR Address 4C000013h Type R/W Reset Value 00000000_00000000h
GLCP_CLK4ACK Register Map
GLCP_SYS_RSTPLL Register Map
GLCP_SYS_RSTPLL Bit Descriptions
GLCP_SYS_RSTPLL Bit Descriptions (Continued)
Table 6-87. Bootstrap Bit Settings and Reset State of GLCP_SYS_RSTPLL (PW1 and IRQ13 = 0)
Table 6-88. Bootstrap Bit Settings and Reset State of GLCP_SYS_RSTPLL (PW1 and IRQ13 vary)
Fout Fin NDIV 1+() MDIV 1+()PDIV 1+()
--------------------------------------------------------------- = Fout 14.318MHz 13 1+() 01+()71+()
---------------------------------- 25.0565MHz==
GLCP_DOTPLL Register Map
GLCP_DOTPLL Bit Descriptions
GLCP_DBGCLKCTL Register Map
GLCP_DBGCLKCTL Bit Descriptions
GLCP_CHIP_REVID Register Map
GLCP_CHIP_REVID Bit Descriptions
GLCP_CNT Register Map
GLCP_CNT Bit Descriptions
GLCP_TH_SD Register Map
GLCP_TH_SD Bit Descriptions
GLCP_TH_SF Register Map
GLCP_TH_SF Bit Descriptions
6.14.3 GLCP IGNNE I/Os
GLCP_TH_OD Register Map
GLCP_TH_OD Bit Descriptions
GLCP_DAC Register Map
GLCP_DAC Bit Descriptions
6.14.5 GLCP Specific MSRs - GLCP Companion Device Interface MSRs
MSR_A20M Register Map
MSR_A20M Bit Descriptions
MSR_INIT Register Map
MSR_INIT Bit Descriptions
MSR_INTAX Register Map
MSR_INTAX Bit Descriptions
6.15 GeodeLink PCI Bridge
Figure 6-58. GL PCI Block Diagram
6.15.1 GeodeLink Interface Block
6.15.2 FIFO/Synchronization Block
6.15.3 Transaction Forwarding Block
Figure 6-59. Atomic MSR Accesses Across the PCI Bus
AMD Geode LX Processor
6.15.4 PCI Bus Interface Block
Table 6-89. Format for Accessing the Internal PCI Configuration Registers
6.15.5 PCI Arbiter
Figure 6-60. Simple Round-Robin
Figure 6-61. Weighted Round-Robin
Table 6-90. PCI Device to AD Bus Mapping
CPU 0 2 1
6.15.6 Exception Handling
6.16 GeodeLink PCI Bridge Register Descriptions
Table 6-91. Standard GeodeLink Device MSRs Summary
Table 6-92. GLPCI Specific Registers Summary
6.16.1 Standard GeodeLink Device (GLD) MSRs
Page
Page
Page
6.16.2 GLPCI Specific Registers
GLPCI_CTRL Register Map
GLPCI_CTRL Bit Descriptions
Page
Page
GLPCI_ARB Register Map
GLPCI_ARB Bit Definitions
GLPCI_ARB Bit Definitions (Continued)
GLPCI_PBUS Register Map
GLPCI_PBUS Bit Descriptions
GLPCI_REN Register Map
GLPCI_REN Bit Descriptions
GLPCI_A0 Register Map
GLPCI_A0 Bit Descriptions
Table 6-93. Region Properties
GLPCI_C0 Register Map
GLPCI_C0 Bit Descriptions
GLPCI_C0 Bit Descriptions (Continued)
GLPCI_E0 Register Map
GLPCI_E0 Bit Descriptions
GLPCI_R0 Register Map
GLPCI_R0 Bit Descriptions
GLPCI_R1 Register Map
GLPCI_R1 Bit Descriptions
GLPCI_R2 Register Map
GLPCI_R2 Bit Descriptions
GLPCI_R3 Register Map
GLPCI_R3 Bit Descriptions
GLPCI_R4 Register Map
GLPCI_R4 Bit Descriptions
GLPCI_R5 Register Map
GLPCI_R5 Bit Descriptions
GLPCI_EXT_MSR Register Map
GLPCI_EXT_MSR Bit Descriptions
GLPCI Spare
GLPCI Spare Bit Descriptions
GLPCI_GPIO Register Map
GLPCI_GPIO Register Bit Descriptions
7.0Electrical Specifications
7.1 Electrical Connections
7.1.1 PWR/GND Connections and Decoupling
7.1.2 NC-Designated Balls
7.1.3 Unused Inputs
7.3 Operating Conditions
Table 7-2 lists the operating conditions for the AMDGeode LX processor.
Note 2. This parameter is calculated as nominal 3%.
Table 7-2. Operating Conditions
Note 3. This parameter is calculated as nominal 5%. Note 4. MVREF = 1/2 VMEM.
7.4 DC Current
7.4.1 Power State Parameter Definitions
7.4.2 Definition and Measurement Techniques of Current Parameters
7.4.3 DC Current Measurements
Figure 7-1. VMEMLX Power Split
Table 7-3. AMD Geode LX 900@1.5W Processor DC Currents
I
Table 7-4. AMD Geode LX 800@0.9W Processor DC Currents
I
Table 7-5. AMD Geode LX 700@0.8W Processor DC Currents
I
Table 7-6. AMD Geode LX 600@0.7W Processor DC Currents
I
7.5 DC Characteristics
Table 7-7. DC Characteristics
Page
Table 7-7. DC Characteristics (Continued)
7.6 AC Characteristics
Figure 7-2. Drive Level and Measurement Points for Switching Characteristics
Figure 7-3. Drive Level and Measurement Points for Switching Characteristics
Table 7-8. System Interface Signals
Figure 7-4. Power Up Sequencing
Figure 7-5. Drive Level and Measurement Points for Switching Characteristics
Table 7-9. PCI Interface Signals
Figure 7-6. Drive Level and Measurement Points for Switching Characteristics
Table 7-10. VIP Interface Signals
Figure 7-7. Drive Level and Measurement Points for Switching Characteristics
Table 7-11. Flat Panel Interface Signals
Table 7-12. CRT Interface Signals
Table 7-13. CRT Display Recommended Operating Conditions
Table 7-14. CRT Display Analog (DAC) Characteristics
Table 7-15. Memory (DDR) Interface Sig nals
Figure 7-8. DDR Write Timing Measurement Points
Figure 7-9. DDR Read Timing Measurement Points
Table 7-16. JTAG Interface Signals
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8.0Instruction Set
8.1 General Instruction Set Format
Table 8-1. General Instruction Set Format
8.1.1 Prefix (Optional)
Table 8-2. Instruction Fields
Table 8-3. Instruction Prefix Summary
8.1.2 Opcode
Table 8-4. w Field Encoding
Table 8-5. d Field Encoding
Table 8-6. s Field Encoding
8.1.3 mod and r/m Byte (Memory Addressing)
Table 8-7. eee Field Encoding
Table 8-8. mod r/m Field Encoding
Table 8-9. General Registers Selected by mod r/m Fields and w Field
Table 8-8. mod r/m Field Encoding (Continued)
8.1.4 reg Field
Table 8-10. reg Field
Table 8-11. sreg2 Field Encoding
Table 8-12. sreg3 Field (FS and GS Segment Register Selection)
8.1.5 s-i-b Byte (Scale, Indexing, Base)
Table 8-13. ss Field Encoding
Table 8-14. index Field Encoding
Table 8-15. mod base Field Encoding
8.2 CPUID Instruction Set
8.2.1 Standard CPUID Levels
Table 8-16. CPUID Instruction with EAX = 00000000h
Table 8-17. CPUID Instruction with EAX = 00000001h
Table 8-18. CPUID Instruction Codes with EAX = 00000000
8.2.2 Extended CPUID Levels
Table 8-19. CPUID Instruction with EAX = 80000000h
Table 8-20. CPUID Instruction with EAX = 80000001h
Table 8-18. CPUID Instruction Codes with EAX = 00000000
Table 8-21. CPUID Instruction Codes with EAX = 80000001h
Table 8-22. CPUID Instruction with EAX = 80000002h, 80000003h, or 80000004h
Table 8-23.
Table 8-24.
8.3 Processor Core Instruction Set
8.3.1 Opcodes
8.3.2 Clock Counts
8.3.3 Flags
Table 8-25. Processor Core Instruction Set Table Legend
Table 8-26. Processor Core Instruction Set
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8.3.4 Non-Standard Processor Core Instructions
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8.4 MMX, FPU, and AMD 3DNow! Technology Instructions Sets
Table 8-27. MMX, FPU, and AMD 3DNow! Instruction Set Table Legend
Table 8-28. MMX Instruction Set
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Table 8-29. FPU Instruction Set
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Table 8-30. AMD 3DNow! Technology Instruction Set
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Table 8-30. AMD 3DNow! Technology Instruction Set (Continued)
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8.4.1 Non-Standard AMD 3DNow! Technology Instructions
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A
Appendix ASupport Documentation
A.1 Order Information
Figure A-1. AMD Geode LX Processors OPN Example
Table A-1. Valid OPN Combinations
A.2 Data Book Revision History
Table A-2. Revision History
Table A-3. Edits to Current Revision
