AMD Geode™ LX Processors Data Book 15
2
Architecture Overview 33234H
2.0Architecture Overview
The CPU Core provides maximum compatibility with the
vast amount of Internet content available while the intelli-
gent integration of several other functions, including graph-
ics, makes the AMD Geode™ LX processor a true system-
level multimedia solution.
The AMD Geode LX processor can be divided into major
functional blocks (as shown in Figure 1-1 on page 11):
•CPU Core
•GeodeLink™ Control Processor
•GeodeLink Interface Units
•GeodeLink Memory Controller
•Graphics Processor
•Display Controller
•Video Processor
— TFT Controller/Video Output Port
•Video Input Port
•GeodeLink PCI Bridge
•Security Block

2.1 CPU Core

The x86 core consists of an Integer Unit, cache memory
subsystem, and an x87 compatible FPU (Floating Point
Unit). The Integer Unit contains the instruction pipeline and
associated logic. The memory subsystem contains the
instruction and data caches, translation look-aside buffers
(TLBs), and an interface to the GeodeLink Interface Units
(GLIUs).
The instruction set supported by the core is a combination
of Intel Pentium® processor, AMDAthlon™ processor, and
AMD Geode LX processor specific instructions. Specifi-
cally, it supports the Pentium, Pentium Pro, AMD 3DNow!™
technology and MMX™ instructions for the AMDAthlo n
processor. It supports a subset of the specialized
AMD Geode LX processor instructions including special
SMM instructions. The CPU Core does not support the
entire Katmai New Instruction (KNI) set as implemented in
the Pentium 3. It does support the MMX instructions for the
AMDAthlon processor, which are a subset of the
Pentium3 KNI instructions.

2.1.1 Integer Unit

The Integer Unit consists of a single issue 8-stage pipeline
and all the necessary support hardware to keep the pipe-
line running efficiently.
The instruction pipeline in the integer unit consists of eight
stages:
1) Instruction Prefetch - Raw instruction data is fetched
from the instruction memory cache.
2) Instruction Pre-decode - Prefix bytes are extracted
from raw instruction data. This decode looks-ahead to
the next instruction and the bubble can be squashed if
the pipeline stalls down stream.
3) Instruction Decode - Performs full decode of instruc-
tion data. Indicates instruction length back to the
Prefetch Unit, allowing the Prefetch Unit to shift the
appropriate number of bytes to the beginning of the
next instruction.
4) Instruction Queue - FIFO containing decoded x86
instructions. Allows Instruction Decode to proceed
even if the pipeline is stalled downstream. Register
reads for data operand address calculations are per-
formed during this stage.
5) Address Calculation #1 - Computes linear address of
operand data (if required) and issues request to the
Data Memory Cache. Microcode can take over the
pipeline and inject a micro-box here if multi-box
instructions require additional data operands.
6) Address Calculation #2 - Operand data (if required)
is returned and set up to the Execution stage with no
bubbles if there was a data cache hit. Segment limit
checking is performed on the data operand address.
The µROM is read for setup to Execution Unit.
7) Execution Unit - Register and/or data memory fetch
fed through the Arithmetic Logic Unit (ALU) for arith-
metic or logical operations. µROM always fires for the
first instruction box down the pipeline. Microcode can
take over the pipeline and insert additional boxes here
if the instruction requires multiple Execution Unit
stages to complete.
8) Writeback - Results of the Execution Unit stages are
written to the register file or to data memory.