608 AMD Geodeā„¢ LX Processors Data Book
Electrical Specifications
33234H
Figure 7-3. Drive Level and Measurement Points for Switching CharacteristicsTable 7-8. System Interface Signals
Symbol Parameter Min Max Unit Comments
tCK SYSREF Cycle time 15.0 INF ns 66 MHz
tCH SYSREF High time 6.0 ns 40% tCK
tCL SYSREF Low time 6.0 ns 40% tCK
tSU1 RESET# Setup time to SYSREF 3 ns Note 1
tH1 RESET# Hold time from SYSREF 1 ns Note 1
tSU2 CIS Setup time to SYSREF 3.0 ns
tH2 CIS Hold time from SYSREF 0 ns
tVAL1 IRQ13 Valid Delay time from SYSREF 2.0 6.0 ns
tVAL2 SUSPA# Valid Delay time from SYSREF 2.0 6.0 ns
tON VIO and VMEM power on after VCORE 0100msNote 2
tMVON MVREF power on after VMEM 0100ms
tRSTX Reset Active time after SYSREF clock stable 100 us For PLL lock
tZOutput drive delay after RESET# released 20 ns
Note 1. RESET# is asynchronous. The setup/hold times stated are for testing purposes that require sequential repeatabil-
ity.
Note 2. For proper powerup of DRGB and flat panel controls, VIO must power up after VCORE. Otherwise, VCORE can be
last.
SYSREF
Outputs
Inputs
50%
Valid Input
Valid Output n+1
Valid Output n
50%
50%
tVAL1,2 Min
tVAL1,2 Max
tSU1,2
tH1,2
tCK
tCH tCL