AMD Geodeā„¢ LX Processors Data Book 459
Video Processor Register Descriptions 33234H
6.8.3.50 32-Bit Panel CRC (CRC32)
6.8.3.51 Video Output Port Configuration (VOP_CONFIG)
VP Memory Offset 468h
Type RO
Reset Value 00000000_00000001h
CRC32 Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
CRC
CRC32 Bit Descriptions
Bit Name Description
63:32 RSVD Reserved. Reads back as 0.
31:0 CRC 32-Bit CRC. 32-Bit Signature when in 32-bit CRC mode. See FP Memory Offset 458h for
additional information.
VP Memory Offset 800h
Type R/W
Reset Value 00000000_00000000h
VOP_CON FIG Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
SPARE
VBI_SWAP
RSVD
RGB_MODE
VALID _SIG
INV_DE_POL
INV_VS_POL
INV_HS_POL
UV_SWAP
VSYNC_SHFT
DIS_DEC
601_MODE
VBI
RSVD
TASK
SGFR
SIGE
SC120X_MODE
422_MODE
EXT_VIP_CODES
VIP_LEVEL
VIP_MODE
VOP_CONFIG Bit Descriptions
Bit Name Description
63:32 RSVD (RO) Reserved (Read Only). Reads back as 0.
31:25 SPARE Spare.
24 VBI SWAP VBI Swap. When set to 1, swap upper and lower bytes of VBI data.
22:23 RSVD Reserved.
21 RGB MODE RGB Mode. Set this bit to 1 if RGB data sent: applicable in 24-bit 601 mode so as to
choose correct blanking data. If this bit is set, then blanking data is 0, otherwise it is YUV
= 10, 80, 80.
20 VALID SIG (RO) Valid Signature (Read Only). If signature enabled, this bit can be read to determine if
the signature is valid.
19 INV DE POL Invert Display Enable Polarity. Set to 1 to invert polarity of display enable (for 601
mode only).