414 AMD Geodeā„¢ LX Processors Data Book
Video Processor Register Descriptions
33234H
Flat Panel
400h R/W Panel Timing Register 1 (PT1) 00000000_00000000h Page 451
408h R/W Panel Timing Register 2 (PT2) 00000000_00000000h Page 453
410h R/W Power Management (PM) 00000000_00000002h Page 454
418h R/W Dither and Frame Rate Control (DFC) 00000000_00000000h Page 456
420h -- Reserved -- --
428h -- Reserved -- --
430h -- Reserved -- --
438h -- Reserved -- --
440h -- Reserved -- --
448h R/W Dither RAM Control and Address (DCA) 00000000_00000000h Page 457
450h R/W Dither Memory Data (DMD) 00000000_00000000h Page 458
458h R/W Panel CRC Signature (CRC) 00000000_00000000h Page 458
460h -- Reserved -- --
468h RO 32-Bit Panel CRC (CRC32) 00000000_00000001h Page459
Video Output Port (VOP)
800h R/W Video Output Port Configuration
(VOP_CONFIG)
00000000_00000000h Page 459
808h RO Video Output Port Signature (VOP_SIG) 00000000_00000000h Page 461
810h-8FFh -- Reserved -- --
1000h-
1FFFh
R/W Video Coefficient RAM (VCR) xxxxxxxx_xxxxxxxxh Page451
Table 6-71. Video Processor Module Configuration Control Registers Summary (Continued)
VP
Memory
Offset Type Register Name Reset Value Reference