AMD Geodeā„¢ LX Processors Data Book 233
GeodeLinkā„¢ Memory Controller Register Descriptions 33234H
6.2.2.13 Counter and CAS Control (MC_PERCNT2)
6.2.2.14 Clocking and Debug (MC_CFCLK_DBUG)
MSR Address 2000001Ch
Type R/W
Reset Value 00000000_00FF00FFh
MC_PERFCNT2 Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
STOP_CNT1
RST_CNT1
STOP_CNT0
RST_CNT0
313029282726252423222120191817161514131211109876543210
RSVD
MC_PERFCNT2 Bit Descriptions
Bit Name Description
63:36 RSVD Reserved.
35 STOP_CNT1 Stop Counter 1. If set, stops counter 1. (Default = 0)
34 RST_CNT1 Reset Counter 1. If set, resets counter 1. (Default = 0)
33 STOP_CNT0 Stop Counter 0. If set, stops counter 0. (Default = 0)
32 RST_CNT0 Reset Counter 0. If set, resets counter 0. (Default = 0)
31:0 RSVD Reserved.
MSR Address 2000001Dh
Type R/W
Reset Value 00000000_00001300h
MC_CFCLK_DBUG Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
B2B_DIS
MTEST_RBEX_EN
MTEST_EN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD
FORCE_PRE
RSVD
TRISTATE_DIS
RSVD
MASK_CKE1
MASK_CKE0
CNTL_MSK1
CNTL_MSK0
ADRS_MSK
RSVD