AMD Geodeā„¢ LX Processors Data Book 159
CPU Core Register Descriptions 33234H
5.5.2.63 Data Memory Subsystem Configuration 0 MSR (DM_CONFIG0_MSR)
MSR Address 00001800h
Type R/W
Reset Value 00000000_00000000h
DM_CONFIG0_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
SNOOPTO
RSVD
WSREQ
RSVD
WCTO
RSVD
WBTO RSVD
WBDIS
313029282726252423222120191817161514131211109876543210
LSLOCK
NOLOCKEVCT
EVCTONRPL
NOFTTBRES
DTCNINV
P4MDIS
DTCDIS
L2TDIS
DCDIS
SPCDEC
WTBRST
WBINVD
NOSMC
NOFWD
BLOCKC
MISSER
LDSER
DM_CONFIG0_MSR Bit Descriptions
Bits Name Description
63:49 RSVD Reserved. (Default = 0)
48 SNOOPTO Snoop Timeout. Allow DM to escape a snoop deadlock by timing out a snoop request to
the DM tag machine.
0: Disable.
1: Enable. (Default)
47 RSVD Reserved. (Default = 0)
46:44 WSREQ Number of Outstanding Write-Serialized Requests. The system must be able to
accept WSREQ+1 cacheline + 2-4 QWORD writes without backing up the bus controller
to prevent a lockup condition in the event of an inbound snoop hit.
000: Unlimited. (Default)
001-111: Binary value.
43 RSVD Reserved. (Default = 0)
42:40 WCTO Write-Combine Timeout. Flushes write-combinable entry from write buffer if it has not
been written for the specified number of clocks.
000: Disable timeout. (Default)
001-111: 2**(4 + WCTO) clocks (32, 64, ..., 2048).
39 RSVD Reserved. (Default = 0)
38:36 WBTO Write-Burst Timeout. Flushes write-burstable entry from write buffer if it has not been
written for the specified number of clocks.
000: Disable timeout. (Default)
001-111: 2**(4 + WBTO) clocks (32, 64, ..., 2048).
35:33 RSVD Reserved. (Default = 0)