402 AMD Geode™ LX Processors Data Book
Video Processor
33234H
6.7.6.5 Operating Modes
BT.656 Mode
BT.656 is the basic standard that specifies the encoding of
the control lines into the data bus. In this mode the sepa-
rate control lines are encoded into the data bus as speci-
fied by Recommendation ITU-R BT.656.
Each line begins with a Start of Active Video (SAV) header,
and ends with an End of Active Video (EAV) header. Each
of these are four-byte sequences beginning with FF, 00,
00. The fourth byte of the header provides important infor-
mation about this line. The bit format of the SAV and EAV
headers is shown in Table 6-62.
The T bit is specified in BT.656 as a constant logic 1. The F
bit indicates Field - 1 for even (also called Field 2), 0 for
odd (Field 1). The V bit indicates Vertical Blanking. The H
bit indicates Horizontal Blanking. Bits P3 through P0 are
protection bits used to detect and correct single-bit errors.
The bits are defined as follows:
P3 = (V + H) + ~T
P2 = (F + H) + ~T
P1 = (F + V) + ~T
P0 = (F + V) + H
Using the above formulas, the bit values are listed in Table
6-63.
VIP 1.1 Compatible Mode
VIP 1.1 compatible mode builds on CBT.656 mode with the
following changes/additions:
— Video Flags T, F, and V can only be changed in the
EAV code. During vertical blanking there must be a
minimum of one SAV/EAV scan line in order to
convey the updated T, F, and V bits.
— Task bit is used to indicate VBI data within the video
stream (T = 0 for VBI Data, T = 1 for active video).
— P3-P0 are ignored.
Table 6-62. SAV/EAV Sequence
Parameter D7D6D5D4D3D2D1D0
Preamble 11111111
00000000
00000000
Status Word T F V H P3 P2 P1 P0
Table 6-63. Protection Bit Values
T F V H P3 P2 P1 P0 Hex
000011100E
0001001113
0010 0 1 0 1 25
0011100038
0100100149
0101010054
0110 0 0 1 0 62
011111117F
1000000080
100111019D
1010 1 0 1 1 AB
10110110B6
11000111C7
11011010DA
1110 1 1 0 0 EC
11110001F1