AMD Geode™ LX Processors Data Book 273
Graphics Processor Register Definitions 33234H
6.4.2.22 Stride (GP_CH3_MODE_STR)
The GP_ CH3_MODE_STR register has multiple uses. The STRIDE field is used to indicate the byte width of the channel 3
bitmaps. Whenever the Y coordinate is incremented, this value is added (or subtracted if the Y bit is set) to (from) the previ-
ous start address to generate the start address for the next line. Stride values up to 64 KB minus one are supported.
The remaining fields of this register describe the type, size and source of the channel 3 data. The output of channel 3 can
be used to replace either source or pattern data into the ROP unit. The PS bit is used to select which pipeline the data will
be placed on. If the FMT indicates that the incoming data is alpha, then the incoming data can be used as alpha data in the
alpha blend unit if the AS bits in the GP_RASTER_MODE (GP Memory Offset 38h[19:17]) register are set to 110. If the
BPP/FMT bits in the GP_RASTER_MODE register (bits [31:28]) indicate the output pixel is 32-bpp, then the incoming alpha
data is converted to 8 bits and is consumed at the rate of one pixel per clock. If the BPP/FMT bits are set for 16-bpp, then
the incoming alpha data is converted to 4 bits and is consumed at the rate of two pixels per clock. Alpha blending is not sup-
ported in 8-bpp mode.
Some operating systems store color data in reverse color order (Blue/Green/Red). This data can be converted into the cor-
rect display order by setting the BGR bit. This works for all input formats except for alpha, so if the incoming data is alpha,
do not set this bit.
Rotation is controlled by the RO bit. If this bit is set, the direction of rotation is determined by the X and Y bits. When this bit
is set, the GP_DST_OFFSET (GP Memory Offset 00h) should point to the upper left corner of the destination and the X
and Y bits in the GP_BLT_MODE (GP Memory Offset 40h[9,8]) should not be set. The output must be left to right, top to
bottom. The output is actually written in horizontal strips, 8, 16 or 32 pixels high and as wide as the output. For 8-bpp rota-
tion, 1K of buffer space is the minimum required to perform the operation. Having 2K available allows data to be prefetched
while the previous tile is being written out. Setting the PL bit limits the buffer size to 1K as it preserves the LUT data in the
other 1K of the buffer. This bit should be set when performing any indexed color BLT or if it is likely that the LUT data that
has been loaded will be needed again for a future BLT. The performance is higher when this bit is not set.
GP_CH3_OFFSET Bit Descriptions
Bit Name Description
31:29 YLSBS YLSBS. Y coordinate of starting pixel within color pattern memory.
28:26 XLSBS XLSBS. X coordinate of starting pixel within color pattern memory.
25 N Nibble Select. Nibble address for 4-bpp pixels/alpha. 0 starts at the leftmost nibble, 1
starts at the rightmost.
24 RSVD Reserved. Write as read.
23:0 OFFSET Offset. Offset from the channel 3 base address to the first source pixel.
GP Memory Offset 64h
Type R/W
Reset Value 00000000h
GP_CH3_MODE_STR Register Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN PS X Y BPP/FMT RO BGR PM PL PE HS RSVD STRIDE
GP_CH3_MODE_STR Bit Descriptions
Bit Name Description
31 EN Enable.
0: Channel 3 is off. Old pipelines behave exactly as they used to.
1: Channel 3 is on. Data is forced into either source or pattern pipeline from channel 3.
30 PS Pipeline Select.
0: Channel 3 data directed to/replaces old pattern pipeline.
1: Channel 3 data directed to/replaces old source pipeline