AMD Geodeā„¢ LX Processors Data Book 483
Video Input Port Register Descriptions 33234H
44h R/W VIP Task B VBI Odd Base/VBI Start
(VIP_TASK_B_VBI_ODD_BASE_VBI_START)
00000000h Page502
48h R/W VIP Task B Data Pitch/Vertical Start Even
(VIP_TASK_B_DATA_PITCH_VERT_START_EVEN)
00000000h Page502
4Ch -- Reserved -- --
50h R/W VIP Task B V Offset (VIP_TASK_B_V_Offset) 00000000h Page503
54h R/W VIP Task B U Offset (VIP_TASK_B_U_OFFSET) 00000000h Page504
58h R/W VIP Ancillary Data/Message Passing/Data Streaming
Buffer1 Base Address (VIP_ANC_MSG_1_BASE)
00000000h Page504
5Ch R/W VIP Ancillary Data/Message Passing/Data Streaming
Buffer 2 Base Address (VIP_ANC_MSG_2_BASE)
00000000h Page505
60h R/W VIP Ancillary Data/Message Passing/Data Streaming
Buffer Size (VIP_ANC_MSG_SIZE)
00000000h Page505
64h -- Reserved -- --
68h R/W VIP Page Offset/ Page Count (VIP_PAGE_OFFSET) 00000000h Page506
6Ch R/W VIP Vertical Start/Stop (VIP_VERT_START_STOP) 00000000h Page 506
70h R/W VIP FIFO Address (VIP_FIFO_R_W_ADDR) 00000000h Page507
74h R/W VIP FIFO Data (VIP_FIFO_DATA) xxxxxxxxh Page 507
78h R/W VIP VSYNC Error Count (VIP_SYNC_ERR_COUNT) 00000000h Page508
7Ch R/W VIP Task A U Even Offset
(VIP_TASK_A_U_EVEN_OFFSET)
00000000h Page508
80h R/W VIP Task A V Even Offset
(VIP_TASK_A_V_EVEN_OFFSET)
00000000h Page509
Table 6-76. VIP Configuration/Control Registers Summary
VIP Memory
Offset Type Register Name Reset Value Reference