AMD LX 600@0.7W, LX 700@0.8W, LX 800@0.9W, LX 900@1.5W DC_ARB_CFG Register Map, DC_ARB_CFG Bit Descriptions

AMD Geode™ LX Processors Data Book 319
Display Controller Register Descriptions 33234H
6.6.3.4 DC Arbitration Configuration (DC_ARB_CFG)
This register contains configuration bits for controlling the priority level of GLIU requests by the DC. It allows high priority to
be enabled under several conditions (see bits [8:1]). These conditions are ORed with other sources of high-priority, includ-
ing the FIFO watermark mechanisms. Settings written to this register take effect immediately. The features in this register
do not affect the DC’s internal prioritization of video vs. graphics data fetches -- just the priority that is presented on the
GeodeLink request. The low priority at VSYNC mechanism (bits [15:9, 0]) takes precedence over all priority mechanisms
except the high priority when line buffer fill in progress” mechanism bit [1].
DC Memory Offset 00Ch
Type R/W
Reset Value 00000000h
DC_ARB_CFG Register Map
313029282726252423222120191817161514131211109876543210
RSVD
LB_LOAD_WM_EN
LB_LOAD_WM LPEN_END_COUNT
HPEN_SB_INV
HPEN_FB_INV_HALFSB
HPEN_FB_INV_SBRD
HPEN_FB_INV
HPEN_1LB_INV HPEN_2LB_INV HPEN_3LB_INV
HPEN_LB_FILL
LPEN_VSYNC
DC_ARB_CFG Bit Descriptions
Bit Name Description
31:21 RSVD Reserved.
20 LB_LOAD_WM_
EN
Line Buffer Load Watermark Enable. When set, allows line buffer loads from the dis-
play FIFO to begin when the display FIFO has at least as much data as defined by the
watermark in bits [19:16] (LB_LOAD_WM). When this bit is cleared, line buffer loads are
not permitted until the display FIFO is full.
19:16 LB_LOAD_WM Line Buffer Load Watermark. When enabled via bit 20 (LB_LOAD_WM_EN), this
watermark determines how much data must be in the DFIFO before a line buffer load is
permitted. This level is set in 256-byte increments.
15:9 LPEN_END_
COUNT
Low Priority End Counter. When bit 0 (LPEN_VSYNC) is set, this field indicates the
number of scan lines after VSYNC that the DC will force its requests to low priority.
Because the line buffers, flicker filter buffers, sync buffer, and data FIFO are all cleared at
VSYNC, this mechanism prevents the DC from spending an inordinate amount of time in
high priority while filling all of these buffers. In most cases this value should be set three
or four lines less than the distance between VSYNC start and V_TOTAL. This value may
need to be lowered if VBI data is enabled.
8 HPEN_SB_INV High Priority Enable when Sync Buffer Invalid. This bit enables the DC to arbitrate in
high priority whenever the synchronizer buffer does not contain valid data.
7 HPEN_FB_INV_
HALFSB
High Priority Enable when Flicker Buffer invalid and Sync Buffer less than Half
Full. This bit enables the DC to arbitrate in high priority whenever the synchronizer buffer
is less than half full and the flicker filter buffer does not contain valid data.
6 HPEN_FB_INV_
SBRD
High Priority Enable when Flicker Buffer invalid and Sync Buffer Being Read. This
bit enables the DC to arbitrate in high priority whenever the synchronizer buffer is being
read and the flicker filter buffer does not contain valid data.
5 HPEN_FB_INV High Priority Enable when Flicker Buffer Invalid. This bit enables the DC to arbitrate
at high priority whenever the flicker filter buffer does not contain valid data.
4 HPEN_1LB_INV High Priority Enable when Any One Line Buffer Invalid. This bit enables the DC to
arbitrate at high priority if any of the three line buffers is invalid. (When the scaler filter is
disabled, only one logical line buffer is used, and the state of the others is ignored.)