AMD LX 600@0.7W, LX 700@0.8W, LX 800@0.9W, LX 900@1.5W MC_CF_BANK45 Register Map, MC_CF_BANK45 Bit Descriptions, MC_CF_BANK67 Register Map, MC_CF_BANK67 Bit Descriptions

224 AMD Geode™ LX Processors Data Book
GeodeLink™ Memory Controller Register Descriptions
33234H
6.2.2.3 Row Addresses Bank4 DIMM0, Bank5 DIMM0 (MC_CF_BANK45)
6.2.2.4 Row Addresses Bank6 DIMM0, Bank7 DIMM0 (MC_CF_BANK67)
MSR Address 20000012h
Type RO
Reset Value xxxxxxxx_xxxxxxxxh
MC_CF_BANK45 Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD MC_CF_BANK5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD MC_CF_BANK4
MC_CF_BANK45 Bit Descriptions
Bit Name Description
63:54 RSVD Reserved. Reads back as 0.
53:32 MC_CF_BANK5 Memory Controller Configuration Bank 5. Open row address (31:10) for Bank5,
DIMM0.
31:22 RSVD Reserved. Reads back as 0.
21:0 MC_CF_BANK4 Memory Controller Configuration Bank 4. Open row address (31:10) for Bank4,
DIMM0.
MSR Address 20000013h
Type RO
Reset Value xxxxxxxx_xxxxxxxxh
MC_CF_BANK67 Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD MC_CF_BANK7
313029282726252423222120191817161514131211109876543210
RSVD MC_CF_BANK6
MC_CF_BANK67 Bit Descriptions
Bit Name Description
63:54 RSVD Reserved. Reads back as 0.
53:32 MC_CF_BANK7 Memory Controller Configuration Bank 7. Open row address (31:10) for Bank7,
DIMM0.
31:22 RSVD Reserved. Reads back as 0.
21:0 MC_CF_BANK6 Memory Controller Configuration Bank 6. Open row address (31:10) for Bank6,
DIMM0.