AMD Geodeā„¢ LX Processors Data Book 493
Video Input Port Register Descriptions 33234H
14 MSG_BERR Message Buffer Error.
0: No error.
1: Message buffer was overwritten. This occurs when both msg buffers are full and a
msg/dstrm packet is received.
Writing a 1 to the bit resets it to 0.
13 B2_FULL MSG Buffer 2 Full.
0: Buffer 2 empty.
1: Buffer 2 full.
Writing a 1 to the bit resets it to 0.
12 B1_FULL MSG Buffer 1 Full.
0: Buffer 1 empty.
1: Buffer 1 full.
Writing a 1 to the bit resets it to 0.
11:10 RSVD Reserved.
9GLWC GLIU Writes Completed.
0: VIP has outstanding GLIU transactions.
1: VIP has completed all outstanding GLIU transactions.
8FE VIP FIFO Empty.
0: VIP FIFO is NOT empty.
1: VIP FIFO is empty.
7:5 RSVD Reserved.
4 F (RO) Field Indication (Read Only). Indicates current status of field being received.
0: Odd field is being received.
1: Even field is being received.
3V (RO) VBLANK Indication (Read Only). Indicates current status of VBLANK being received.
0: Active video.
1: Vertical blanking.
2:0 Run Status (RO) Run Status (Read Only). Indicates active data types received.
Bit 2: Indicates that an ancillary packet has been received.
Bit 1: Indicates that a VBI packet has been received.
Bit 0: Indicates that a video packet or Msg/Data Streaming packet has been received.
Writing a 1 to a bit resets it to 0. These bits are enabled when the corresponding DT_EN
bits are set in the VIP Control 1 register (VIP Memory Offset 00h) along with the
VIP_MODE bits.
VIP_STATUS Bit Descriptions (Continued)
Bit Name Description