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DS21Q55

Register Name:

TCICE3

 

 

 

 

 

 

 

 

Register Description:

Transmit Channel Idle Code Enable Register 3

 

 

 

Register Address:

82h

 

 

 

 

 

 

 

 

Bit #

7

6

 

5

4

3

2

 

1

0

 

Name

 

CH24

CH23

 

CH22

CH21

CH20

CH19

 

CH18

CH17

 

Default

 

0

0

 

0

0

0

0

 

0

0

 

Bits 0 to 7/Transmit Channels 17 to 24 Code Insertion Control Bits (CH17 to CH24).

 

 

 

0 = do not insert data from the idle code array into the transmit data stream

 

 

 

 

1 = insert data from the idle code array into the transmit data stream

 

 

 

Register Name:

TCICE4

 

 

 

 

 

 

 

 

Register Description:

Transmit Channel Idle Code Enable Register 4

 

 

 

Register Address:

83h

 

 

 

 

 

 

 

 

Bit #

Name

Default

7

6

5

4

3

2

1

0

CH32

CH31

CH30

CH29

CH28

CH27

CH26

CH25

0

0

0

0

0

0

0

0

Bits 0 to 7/Transmit Channels 25 to 32 Code Insertion Control Bits (CH25 to CH32).

0 = do not insert data from the idle code array into the transmit data stream 1 = insert data from the idle code array into the transmit data stream

The receive-channel idle-code enable registers (RCICE1 /2/3/4) are used to determine which of the 24 T1 or 32 E1 channels from the backplane to the T1 or E1 line should be overwritten with the code placed in the per-channel code array.

Register Name:

RCICE1

 

 

 

 

 

 

Register Description:

Receive Channel Idle Code Enable Register 1

 

 

Register Address:

84h

 

 

 

 

 

 

Bit #

7

6

 

5

4

3

2

1

0

Name

CH8

CH7

 

CH6

CH5

CH4

CH3

CH2

CH1

Default

0

0

 

0

0

0

0

0

0

Bits 0 to 7/Receive Channels 1 to 8 Code Insertion Control Bits (CH1 to CH8). 0 = do not insert data from the idle code array into the receive data stream 1 = insert data from the idle code array into the receive data stream

Register Na me:

RCICE2

 

 

 

 

 

 

Register Description:

Receive Channel Idle Code Enable Register 2

 

 

Register Address:

85h

 

 

 

 

 

 

Bit #

7

6

 

5

4

3

2

1

0

Name

CH16

CH15

 

CH14

CH13

CH12

CH11

CH10

CH9

Default

0

0

 

0

0

0

0

0

0

Bits 0 to 7/Receive Channels 9 to 16 Code Insertion Control Bits (CH9 to CH16). 0 = do not insert data from the idle code array into the receive data stream 1 = insert data from the idle code array into the receive data stream

101 of 248

012103

Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated

information.

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Maxim DS21Q55 specifications TCICE3, TCICE4, RCICE1, RCICE2